2 * Copyright 2013 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 * The RGMII PHYs are provided by the two on-board PHY connected to
9 * dTSEC instances 4 and 5. The SGMII PHYs are provided by one on-board
10 * PHY or by the standard four-port SGMII riser card (VSC).
15 #include <asm/fsl_serdes.h>
16 #include <asm/immap_85xx.h>
20 #include <asm/fsl_dtsec.h>
22 #include "../common/fman.h"
23 #include "../common/qixis.h"
25 #include "t1040qds_qixis.h"
27 #ifdef CONFIG_FMAN_ENET
28 /* - In T1040 there are only 8 SERDES lanes, spread across 2 SERDES banks.
29 * Bank 1 -> Lanes A, B, C, D
30 * Bank 2 -> Lanes E, F, G, H
33 /* Mapping of 8 SERDES lanes to T1040 QDS board slots. A value of '0' here
34 * means that the mapping must be determined dynamically, or that the lane
35 * maps to something other than a board slot.
37 static u8 lane_to_slot[] = {
38 0, 0, 0, 0, 0, 0, 0, 0
41 /* On the Vitesse VSC8234XHG SGMII riser card there are 4 SGMII PHYs
44 static int riser_phy_addr[] = {
45 CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR,
46 CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR,
47 CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR,
48 CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR,
51 /* Slot2 does not have EMI connections */
52 #define EMI_NONE 0xFFFFFFFF
63 static int mdio_mux[NUM_FM_PORTS];
65 static const char * const mdio_names[] = {
76 struct t1040_qds_mdio {
78 struct mii_dev *realbus;
81 static const char *t1040_qds_mdio_name_for_muxval(u8 muxval)
83 return mdio_names[muxval];
86 struct mii_dev *mii_dev_for_muxval(u8 muxval)
89 const char *name = t1040_qds_mdio_name_for_muxval(muxval);
92 printf("No bus for muxval %x\n", muxval);
96 bus = miiphy_get_dev_by_name(name);
99 printf("No bus by name %s\n", name);
106 static void t1040_qds_mux_mdio(u8 muxval)
110 brdcfg4 = QIXIS_READ(brdcfg[4]);
111 brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
112 brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
113 QIXIS_WRITE(brdcfg[4], brdcfg4);
117 static int t1040_qds_mdio_read(struct mii_dev *bus, int addr, int devad,
120 struct t1040_qds_mdio *priv = bus->priv;
122 t1040_qds_mux_mdio(priv->muxval);
124 return priv->realbus->read(priv->realbus, addr, devad, regnum);
127 static int t1040_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
128 int regnum, u16 value)
130 struct t1040_qds_mdio *priv = bus->priv;
132 t1040_qds_mux_mdio(priv->muxval);
134 return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
137 static int t1040_qds_mdio_reset(struct mii_dev *bus)
139 struct t1040_qds_mdio *priv = bus->priv;
141 return priv->realbus->reset(priv->realbus);
144 static int t1040_qds_mdio_init(char *realbusname, u8 muxval)
146 struct t1040_qds_mdio *pmdio;
147 struct mii_dev *bus = mdio_alloc();
150 printf("Failed to allocate t1040_qds MDIO bus\n");
154 pmdio = malloc(sizeof(*pmdio));
156 printf("Failed to allocate t1040_qds private data\n");
161 bus->read = t1040_qds_mdio_read;
162 bus->write = t1040_qds_mdio_write;
163 bus->reset = t1040_qds_mdio_reset;
164 sprintf(bus->name, t1040_qds_mdio_name_for_muxval(muxval));
166 pmdio->realbus = miiphy_get_dev_by_name(realbusname);
168 if (!pmdio->realbus) {
169 printf("No bus with name %s\n", realbusname);
175 pmdio->muxval = muxval;
178 return mdio_register(bus);
182 * Initialize the lane_to_slot[] array.
184 * On the T1040QDS board the mapping is controlled by ?? register.
186 static void initialize_lane_to_slot(void)
188 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
189 int serdes1_prtcl = (in_be32(&gur->rcwsr[4]) &
190 FSL_CORENET2_RCWSR4_SRDS1_PRTCL)
191 >> FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
193 QIXIS_WRITE(cms[0], 0x07);
195 switch (serdes1_prtcl) {
256 printf("qds: Fman: Unsupported SerDes Protocol 0x%02x\n",
263 * Given the following ...
265 * 1) A pointer to an Fman Ethernet node (as identified by the 'compat'
266 * compatible string and 'addr' physical address)
270 * ... update the phy-handle property of the Ethernet node to point to the
271 * right PHY. This assumes that we already know the PHY for each port.
273 * The offset of the Fman Ethernet node is also passed in for convenience, but
274 * it is not used, and we recalculate the offset anyway.
276 * Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC.
277 * Inside the Fman, "ports" are things that connect to MACs. We only call them
278 * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs
279 * and ports are the same thing.
282 void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
283 enum fm_port port, int offset)
285 phy_interface_t intf = fm_info_get_enet_if(port);
288 /* The RGMII PHY is identified by the MAC connected to it */
289 if (intf == PHY_INTERFACE_MODE_RGMII) {
290 sprintf(phy, "rgmii_phy%u", port == FM1_DTSEC4 ? 1 : 2);
291 fdt_set_phy_handle(fdt, compat, addr, phy);
294 /* The SGMII PHY is identified by the MAC connected to it */
295 if (intf == PHY_INTERFACE_MODE_SGMII) {
296 int lane = serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC1
301 slot = lane_to_slot[lane];
303 /* Slot housing a SGMII riser card */
304 sprintf(phy, "phy_s%x_%02x", slot,
305 (fm_info_get_phy_address(port - FM1_DTSEC1)-
306 CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR + 1));
307 fdt_set_phy_handle(fdt, compat, addr, phy);
312 void fdt_fixup_board_enet(void *fdt)
316 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
317 idx = i - FM1_DTSEC1;
318 switch (fm_info_get_enet_if(i)) {
319 case PHY_INTERFACE_MODE_SGMII:
320 lane = serdes_get_first_lane(FSL_SRDS_1,
321 SGMII_FM1_DTSEC1 + idx);
325 switch (mdio_mux[i]) {
327 fdt_status_okay_by_alias(fdt, "emi1_slot3");
330 fdt_status_okay_by_alias(fdt, "emi1_slot5");
333 fdt_status_okay_by_alias(fdt, "emi1_slot6");
336 fdt_status_okay_by_alias(fdt, "emi1_slot7");
340 case PHY_INTERFACE_MODE_RGMII:
342 fdt_status_okay_by_alias(fdt, "emi1_rgmii0");
345 fdt_status_okay_by_alias(fdt, "emi1_rgmii1");
352 #endif /* #ifdef CONFIG_FMAN_ENET */
354 static void set_brdcfg9_for_gtx_clk(void)
357 brdcfg9 = QIXIS_READ(brdcfg[9]);
358 /* Initializing EPHY2 clock to RGMII mode */
359 brdcfg9 &= ~(BRDCFG9_EPHY2_MASK);
360 brdcfg9 |= (BRDCFG9_EPHY2_VAL);
361 QIXIS_WRITE(brdcfg[9], brdcfg9);
364 void t1040_handle_phy_interface_sgmii(int i)
367 idx = i - FM1_DTSEC1;
368 lane = serdes_get_first_lane(FSL_SRDS_1,
369 SGMII_FM1_DTSEC1 + idx);
373 slot = lane_to_slot[lane];
377 mdio_mux[i] = EMI1_SLOT1;
378 fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
382 fm_info_set_phy_address(i, riser_phy_addr[0]);
384 fm_info_set_phy_address(i, riser_phy_addr[1]);
386 mdio_mux[i] = EMI1_SLOT3;
388 fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
391 mdio_mux[i] = EMI1_SLOT4;
392 fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
395 /* Slot housing a SGMII riser card? */
396 fm_info_set_phy_address(i, riser_phy_addr[0]);
397 mdio_mux[i] = EMI1_SLOT5;
398 fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
401 /* Slot housing a SGMII riser card? */
402 fm_info_set_phy_address(i, riser_phy_addr[0]);
403 mdio_mux[i] = EMI1_SLOT6;
404 fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
408 fm_info_set_phy_address(i, riser_phy_addr[0]);
410 fm_info_set_phy_address(i, riser_phy_addr[1]);
412 fm_info_set_phy_address(i, riser_phy_addr[2]);
414 mdio_mux[i] = EMI1_SLOT7;
415 fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
420 fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
422 void t1040_handle_phy_interface_rgmii(int i)
424 fm_info_set_phy_address(i, i == FM1_DTSEC5 ?
425 CONFIG_SYS_FM1_DTSEC5_PHY_ADDR :
426 CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
427 mdio_mux[i] = (i == FM1_DTSEC5) ? EMI1_RGMII1 :
429 fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
432 int board_eth_init(bd_t *bis)
434 #ifdef CONFIG_FMAN_ENET
435 struct memac_mdio_info memac_mdio_info;
438 printf("Initializing Fman\n");
439 set_brdcfg9_for_gtx_clk();
441 initialize_lane_to_slot();
443 /* Initialize the mdio_mux array so we can recognize empty elements */
444 for (i = 0; i < NUM_FM_PORTS; i++)
445 mdio_mux[i] = EMI_NONE;
447 memac_mdio_info.regs =
448 (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
449 memac_mdio_info.name = DEFAULT_FM_MDIO_NAME;
451 /* Register the real 1G MDIO bus */
452 fm_memac_mdio_init(bis, &memac_mdio_info);
454 /* Register the muxing front-ends to the MDIO buses */
455 t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII0);
456 t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
457 t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
458 t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
459 t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
460 t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
461 t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT6);
462 t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7);
465 * Program on board RGMII PHY addresses. If the SGMII Riser
466 * card used, we'll override the PHY address later. For any DTSEC that
467 * is RGMII, we'll also override its PHY address later. We assume that
468 * DTSEC4 and DTSEC5 are used for RGMII.
470 fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
471 fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_DTSEC5_PHY_ADDR);
473 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
474 switch (fm_info_get_enet_if(i)) {
475 case PHY_INTERFACE_MODE_QSGMII:
477 case PHY_INTERFACE_MODE_SGMII:
478 t1040_handle_phy_interface_sgmii(i);
481 case PHY_INTERFACE_MODE_RGMII:
482 /* Only DTSEC4 and DTSEC5 can be routed to RGMII */
483 t1040_handle_phy_interface_rgmii(i);
493 return pci_eth_init(bis);