2 * Copyright 2013 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 * The RGMII PHYs are provided by the two on-board PHY connected to
9 * dTSEC instances 4 and 5. The SGMII PHYs are provided by one on-board
10 * PHY or by the standard four-port SGMII riser card (VSC).
15 #include <asm/fsl_serdes.h>
16 #include <asm/immap_85xx.h>
20 #include <fsl_dtsec.h>
23 #include "../common/fman.h"
24 #include "../common/qixis.h"
26 #include "t1040qds_qixis.h"
28 #ifdef CONFIG_FMAN_ENET
29 /* - In T1040 there are only 8 SERDES lanes, spread across 2 SERDES banks.
30 * Bank 1 -> Lanes A, B, C, D
31 * Bank 2 -> Lanes E, F, G, H
34 /* Mapping of 8 SERDES lanes to T1040 QDS board slots. A value of '0' here
35 * means that the mapping must be determined dynamically, or that the lane
36 * maps to something other than a board slot.
38 static u8 lane_to_slot[] = {
39 0, 0, 0, 0, 0, 0, 0, 0
42 /* On the Vitesse VSC8234XHG SGMII riser card there are 4 SGMII PHYs
45 static int riser_phy_addr[] = {
46 CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR,
47 CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR,
48 CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR,
49 CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR,
52 /* Slot2 does not have EMI connections */
53 #define EMI_NONE 0xFFFFFFFF
64 static int mdio_mux[NUM_FM_PORTS];
66 static const char * const mdio_names[] = {
77 struct t1040_qds_mdio {
79 struct mii_dev *realbus;
82 static const char *t1040_qds_mdio_name_for_muxval(u8 muxval)
84 return mdio_names[muxval];
87 struct mii_dev *mii_dev_for_muxval(u8 muxval)
90 const char *name = t1040_qds_mdio_name_for_muxval(muxval);
93 printf("No bus for muxval %x\n", muxval);
97 bus = miiphy_get_dev_by_name(name);
100 printf("No bus by name %s\n", name);
107 static void t1040_qds_mux_mdio(u8 muxval)
111 brdcfg4 = QIXIS_READ(brdcfg[4]);
112 brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
113 brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
114 QIXIS_WRITE(brdcfg[4], brdcfg4);
118 static int t1040_qds_mdio_read(struct mii_dev *bus, int addr, int devad,
121 struct t1040_qds_mdio *priv = bus->priv;
123 t1040_qds_mux_mdio(priv->muxval);
125 return priv->realbus->read(priv->realbus, addr, devad, regnum);
128 static int t1040_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
129 int regnum, u16 value)
131 struct t1040_qds_mdio *priv = bus->priv;
133 t1040_qds_mux_mdio(priv->muxval);
135 return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
138 static int t1040_qds_mdio_reset(struct mii_dev *bus)
140 struct t1040_qds_mdio *priv = bus->priv;
142 return priv->realbus->reset(priv->realbus);
145 static int t1040_qds_mdio_init(char *realbusname, u8 muxval)
147 struct t1040_qds_mdio *pmdio;
148 struct mii_dev *bus = mdio_alloc();
151 printf("Failed to allocate t1040_qds MDIO bus\n");
155 pmdio = malloc(sizeof(*pmdio));
157 printf("Failed to allocate t1040_qds private data\n");
162 bus->read = t1040_qds_mdio_read;
163 bus->write = t1040_qds_mdio_write;
164 bus->reset = t1040_qds_mdio_reset;
165 sprintf(bus->name, t1040_qds_mdio_name_for_muxval(muxval));
167 pmdio->realbus = miiphy_get_dev_by_name(realbusname);
169 if (!pmdio->realbus) {
170 printf("No bus with name %s\n", realbusname);
176 pmdio->muxval = muxval;
179 return mdio_register(bus);
183 * Initialize the lane_to_slot[] array.
185 * On the T1040QDS board the mapping is controlled by ?? register.
187 static void initialize_lane_to_slot(void)
189 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
190 int serdes1_prtcl = (in_be32(&gur->rcwsr[4]) &
191 FSL_CORENET2_RCWSR4_SRDS1_PRTCL)
192 >> FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
194 QIXIS_WRITE(cms[0], 0x07);
196 switch (serdes1_prtcl) {
260 printf("qds: Fman: Unsupported SerDes Protocol 0x%02x\n",
267 * Given the following ...
269 * 1) A pointer to an Fman Ethernet node (as identified by the 'compat'
270 * compatible string and 'addr' physical address)
274 * ... update the phy-handle property of the Ethernet node to point to the
275 * right PHY. This assumes that we already know the PHY for each port.
277 * The offset of the Fman Ethernet node is also passed in for convenience, but
278 * it is not used, and we recalculate the offset anyway.
280 * Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC.
281 * Inside the Fman, "ports" are things that connect to MACs. We only call them
282 * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs
283 * and ports are the same thing.
286 void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
287 enum fm_port port, int offset)
289 phy_interface_t intf = fm_info_get_enet_if(port);
292 /* The RGMII PHY is identified by the MAC connected to it */
293 if (intf == PHY_INTERFACE_MODE_RGMII) {
294 sprintf(phy, "rgmii_phy%u", port == FM1_DTSEC4 ? 1 : 2);
295 fdt_set_phy_handle(fdt, compat, addr, phy);
298 /* The SGMII PHY is identified by the MAC connected to it */
299 if (intf == PHY_INTERFACE_MODE_SGMII) {
300 int lane = serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC1
305 slot = lane_to_slot[lane];
307 /* Slot housing a SGMII riser card */
308 sprintf(phy, "phy_s%x_%02x", slot,
309 (fm_info_get_phy_address(port - FM1_DTSEC1)-
310 CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR + 1));
311 fdt_set_phy_handle(fdt, compat, addr, phy);
316 void fdt_fixup_board_enet(void *fdt)
320 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
321 idx = i - FM1_DTSEC1;
322 switch (fm_info_get_enet_if(i)) {
323 case PHY_INTERFACE_MODE_SGMII:
324 lane = serdes_get_first_lane(FSL_SRDS_1,
325 SGMII_FM1_DTSEC1 + idx);
329 switch (mdio_mux[i]) {
331 fdt_status_okay_by_alias(fdt, "emi1_slot3");
334 fdt_status_okay_by_alias(fdt, "emi1_slot5");
337 fdt_status_okay_by_alias(fdt, "emi1_slot6");
340 fdt_status_okay_by_alias(fdt, "emi1_slot7");
344 case PHY_INTERFACE_MODE_RGMII:
346 fdt_status_okay_by_alias(fdt, "emi1_rgmii0");
349 fdt_status_okay_by_alias(fdt, "emi1_rgmii1");
356 #endif /* #ifdef CONFIG_FMAN_ENET */
358 static void set_brdcfg9_for_gtx_clk(void)
361 brdcfg9 = QIXIS_READ(brdcfg[9]);
362 /* Initializing EPHY2 clock to RGMII mode */
363 brdcfg9 &= ~(BRDCFG9_EPHY2_MASK);
364 brdcfg9 |= (BRDCFG9_EPHY2_VAL);
365 QIXIS_WRITE(brdcfg[9], brdcfg9);
368 void t1040_handle_phy_interface_sgmii(int i)
371 idx = i - FM1_DTSEC1;
372 lane = serdes_get_first_lane(FSL_SRDS_1,
373 SGMII_FM1_DTSEC1 + idx);
377 slot = lane_to_slot[lane];
381 mdio_mux[i] = EMI1_SLOT1;
382 fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
386 fm_info_set_phy_address(i, riser_phy_addr[0]);
388 fm_info_set_phy_address(i, riser_phy_addr[1]);
390 mdio_mux[i] = EMI1_SLOT3;
392 fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
395 mdio_mux[i] = EMI1_SLOT4;
396 fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
399 /* Slot housing a SGMII riser card? */
400 fm_info_set_phy_address(i, riser_phy_addr[0]);
401 mdio_mux[i] = EMI1_SLOT5;
402 fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
405 /* Slot housing a SGMII riser card? */
406 fm_info_set_phy_address(i, riser_phy_addr[0]);
407 mdio_mux[i] = EMI1_SLOT6;
408 fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
412 fm_info_set_phy_address(i, riser_phy_addr[0]);
414 fm_info_set_phy_address(i, riser_phy_addr[1]);
416 fm_info_set_phy_address(i, riser_phy_addr[2]);
418 fm_info_set_phy_address(i, riser_phy_addr[3]);
420 mdio_mux[i] = EMI1_SLOT7;
421 fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
426 fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
428 void t1040_handle_phy_interface_rgmii(int i)
430 fm_info_set_phy_address(i, i == FM1_DTSEC5 ?
431 CONFIG_SYS_FM1_DTSEC5_PHY_ADDR :
432 CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
433 mdio_mux[i] = (i == FM1_DTSEC5) ? EMI1_RGMII1 :
435 fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
438 int board_eth_init(bd_t *bis)
440 #ifdef CONFIG_FMAN_ENET
441 struct memac_mdio_info memac_mdio_info;
443 #ifdef CONFIG_VSC9953
446 phy_interface_t phy_int;
450 printf("Initializing Fman\n");
451 set_brdcfg9_for_gtx_clk();
453 initialize_lane_to_slot();
455 /* Initialize the mdio_mux array so we can recognize empty elements */
456 for (i = 0; i < NUM_FM_PORTS; i++)
457 mdio_mux[i] = EMI_NONE;
459 memac_mdio_info.regs =
460 (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
461 memac_mdio_info.name = DEFAULT_FM_MDIO_NAME;
463 /* Register the real 1G MDIO bus */
464 fm_memac_mdio_init(bis, &memac_mdio_info);
466 /* Register the muxing front-ends to the MDIO buses */
467 t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII0);
468 t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
469 t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
470 t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
471 t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
472 t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
473 t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT6);
474 t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7);
477 * Program on board RGMII PHY addresses. If the SGMII Riser
478 * card used, we'll override the PHY address later. For any DTSEC that
479 * is RGMII, we'll also override its PHY address later. We assume that
480 * DTSEC4 and DTSEC5 are used for RGMII.
482 fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
483 fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_DTSEC5_PHY_ADDR);
485 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
486 switch (fm_info_get_enet_if(i)) {
487 case PHY_INTERFACE_MODE_QSGMII:
488 fm_info_set_mdio(i, NULL);
490 case PHY_INTERFACE_MODE_SGMII:
491 t1040_handle_phy_interface_sgmii(i);
494 case PHY_INTERFACE_MODE_RGMII:
495 /* Only DTSEC4 and DTSEC5 can be routed to RGMII */
496 t1040_handle_phy_interface_rgmii(i);
503 #ifdef CONFIG_VSC9953
504 for (i = 0; i < VSC9953_MAX_PORTS; i++) {
507 phy_int = PHY_INTERFACE_MODE_NONE;
513 lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_A);
514 /* PHYs connected over QSGMII */
516 phy_addr = CONFIG_SYS_FM1_QSGMII21_PHY_ADDR +
518 phy_int = PHY_INTERFACE_MODE_QSGMII;
521 lane = serdes_get_first_lane(FSL_SRDS_1,
527 /* PHYs connected over QSGMII */
528 if (i != 3 || lane_to_slot[lane] == 7)
529 phy_addr = CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR
532 phy_addr = CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR;
533 phy_int = PHY_INTERFACE_MODE_SGMII;
539 lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_B);
540 /* PHYs connected over QSGMII */
542 phy_addr = CONFIG_SYS_FM1_QSGMII11_PHY_ADDR +
544 phy_int = PHY_INTERFACE_MODE_QSGMII;
547 lane = serdes_get_first_lane(FSL_SRDS_1,
549 /* PHYs connected over SGMII */
551 phy_addr = CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR
553 phy_int = PHY_INTERFACE_MODE_SGMII;
557 if (serdes_get_first_lane(FSL_SRDS_1,
558 SGMII_FM1_DTSEC1) < 0)
559 /* FM1@DTSEC1 is connected to SW1@PORT8 */
560 vsc9953_port_enable(i);
563 if (serdes_get_first_lane(FSL_SRDS_1,
564 SGMII_FM1_DTSEC2) < 0) {
565 /* Enable L2 On MAC2 using SCFG */
566 struct ccsr_scfg *scfg = (struct ccsr_scfg *)
567 CONFIG_SYS_MPC85xx_SCFG;
569 out_be32(&scfg->esgmiiselcr,
570 in_be32(&scfg->esgmiiselcr) |
572 vsc9953_port_enable(i);
578 bus = mii_dev_for_muxval(lane_to_slot[lane]);
579 vsc9953_port_info_set_mdio(i, bus);
580 vsc9953_port_enable(i);
582 vsc9953_port_info_set_phy_address(i, phy_addr);
583 vsc9953_port_info_set_phy_int(i, phy_int);
590 return pci_eth_init(bis);