common: Drop image.h from common header
[oweals/u-boot.git] / board / freescale / t1040qds / eth.c
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright 2013 Freescale Semiconductor, Inc.
4  */
5
6 /*
7  * The RGMII PHYs are provided by the two on-board PHY connected to
8  * dTSEC instances 4 and 5. The SGMII PHYs are provided by one on-board
9  * PHY or by the standard four-port SGMII riser card (VSC).
10  */
11
12 #include <common.h>
13 #include <fdt_support.h>
14 #include <net.h>
15 #include <netdev.h>
16 #include <asm/fsl_serdes.h>
17 #include <asm/immap_85xx.h>
18 #include <fm_eth.h>
19 #include <fsl_mdio.h>
20 #include <malloc.h>
21 #include <fsl_dtsec.h>
22 #include <vsc9953.h>
23
24 #include "../common/fman.h"
25 #include "../common/qixis.h"
26
27 #include "t1040qds_qixis.h"
28
29 #ifdef CONFIG_FMAN_ENET
30  /* - In T1040 there are only 8 SERDES lanes, spread across 2 SERDES banks.
31  *   Bank 1 -> Lanes A, B, C, D
32  *   Bank 2 -> Lanes E, F, G, H
33  */
34
35  /* Mapping of 8 SERDES lanes to T1040 QDS board slots. A value of '0' here
36   * means that the mapping must be determined dynamically, or that the lane
37   * maps to something other than a board slot.
38   */
39 static u8 lane_to_slot[] = {
40         0, 0, 0, 0, 0, 0, 0, 0
41 };
42
43 /* On the Vitesse VSC8234XHG SGMII riser card there are 4 SGMII PHYs
44  * housed.
45  */
46 static int riser_phy_addr[] = {
47         CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR,
48         CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR,
49         CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR,
50         CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR,
51 };
52
53 /* Slot2 does not have EMI connections */
54 #define EMI_NONE        0xFFFFFFFF
55 #define EMI1_RGMII0     0
56 #define EMI1_RGMII1     1
57 #define EMI1_SLOT1      2
58 #define EMI1_SLOT3      3
59 #define EMI1_SLOT4      4
60 #define EMI1_SLOT5      5
61 #define EMI1_SLOT6      6
62 #define EMI1_SLOT7      7
63 #define EMI2            8
64
65 static int mdio_mux[NUM_FM_PORTS];
66
67 static const char * const mdio_names[] = {
68         "T1040_QDS_MDIO0",
69         "T1040_QDS_MDIO1",
70         "T1040_QDS_MDIO2",
71         "T1040_QDS_MDIO3",
72         "T1040_QDS_MDIO4",
73         "T1040_QDS_MDIO5",
74         "T1040_QDS_MDIO6",
75         "T1040_QDS_MDIO7",
76 };
77
78 struct t1040_qds_mdio {
79         u8 muxval;
80         struct mii_dev *realbus;
81 };
82
83 static const char *t1040_qds_mdio_name_for_muxval(u8 muxval)
84 {
85         return mdio_names[muxval];
86 }
87
88 struct mii_dev *mii_dev_for_muxval(u8 muxval)
89 {
90         struct mii_dev *bus;
91         const char *name = t1040_qds_mdio_name_for_muxval(muxval);
92
93         if (!name) {
94                 printf("No bus for muxval %x\n", muxval);
95                 return NULL;
96         }
97
98         bus = miiphy_get_dev_by_name(name);
99
100         if (!bus) {
101                 printf("No bus by name %s\n", name);
102                 return NULL;
103         }
104
105         return bus;
106 }
107
108 static void t1040_qds_mux_mdio(u8 muxval)
109 {
110         u8 brdcfg4;
111         if (muxval <= 7) {
112                 brdcfg4 = QIXIS_READ(brdcfg[4]);
113                 brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
114                 brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
115                 QIXIS_WRITE(brdcfg[4], brdcfg4);
116         }
117 }
118
119 static int t1040_qds_mdio_read(struct mii_dev *bus, int addr, int devad,
120                                 int regnum)
121 {
122         struct t1040_qds_mdio *priv = bus->priv;
123
124         t1040_qds_mux_mdio(priv->muxval);
125
126         return priv->realbus->read(priv->realbus, addr, devad, regnum);
127 }
128
129 static int t1040_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
130                                 int regnum, u16 value)
131 {
132         struct t1040_qds_mdio *priv = bus->priv;
133
134         t1040_qds_mux_mdio(priv->muxval);
135
136         return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
137 }
138
139 static int t1040_qds_mdio_reset(struct mii_dev *bus)
140 {
141         struct t1040_qds_mdio *priv = bus->priv;
142
143         return priv->realbus->reset(priv->realbus);
144 }
145
146 static int t1040_qds_mdio_init(char *realbusname, u8 muxval)
147 {
148         struct t1040_qds_mdio *pmdio;
149         struct mii_dev *bus = mdio_alloc();
150
151         if (!bus) {
152                 printf("Failed to allocate t1040_qds MDIO bus\n");
153                 return -1;
154         }
155
156         pmdio = malloc(sizeof(*pmdio));
157         if (!pmdio) {
158                 printf("Failed to allocate t1040_qds private data\n");
159                 free(bus);
160                 return -1;
161         }
162
163         bus->read = t1040_qds_mdio_read;
164         bus->write = t1040_qds_mdio_write;
165         bus->reset = t1040_qds_mdio_reset;
166         strcpy(bus->name, t1040_qds_mdio_name_for_muxval(muxval));
167
168         pmdio->realbus = miiphy_get_dev_by_name(realbusname);
169
170         if (!pmdio->realbus) {
171                 printf("No bus with name %s\n", realbusname);
172                 free(bus);
173                 free(pmdio);
174                 return -1;
175         }
176
177         pmdio->muxval = muxval;
178         bus->priv = pmdio;
179
180         return mdio_register(bus);
181 }
182
183 /*
184  * Initialize the lane_to_slot[] array.
185  *
186  * On the T1040QDS board the mapping is controlled by ?? register.
187  */
188 static void initialize_lane_to_slot(void)
189 {
190         ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
191         int serdes1_prtcl = (in_be32(&gur->rcwsr[4]) &
192                                 FSL_CORENET2_RCWSR4_SRDS1_PRTCL)
193                 >> FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
194
195         QIXIS_WRITE(cms[0], 0x07);
196
197         switch (serdes1_prtcl) {
198         case 0x60:
199         case 0x66:
200         case 0x67:
201         case 0x69:
202                 lane_to_slot[1] = 7;
203                 lane_to_slot[2] = 6;
204                 lane_to_slot[3] = 5;
205                 break;
206         case 0x86:
207                 lane_to_slot[1] = 7;
208                 lane_to_slot[2] = 7;
209                 lane_to_slot[3] = 7;
210                 break;
211         case 0x87:
212                 lane_to_slot[1] = 7;
213                 lane_to_slot[2] = 7;
214                 lane_to_slot[3] = 7;
215                 lane_to_slot[7] = 7;
216                 break;
217         case 0x89:
218                 lane_to_slot[1] = 7;
219                 lane_to_slot[2] = 7;
220                 lane_to_slot[3] = 7;
221                 lane_to_slot[6] = 7;
222                 lane_to_slot[7] = 7;
223                 break;
224         case 0x8d:
225                 lane_to_slot[1] = 7;
226                 lane_to_slot[2] = 7;
227                 lane_to_slot[3] = 7;
228                 lane_to_slot[5] = 3;
229                 lane_to_slot[6] = 3;
230                 lane_to_slot[7] = 3;
231                 break;
232         case 0x8F:
233         case 0x85:
234                 lane_to_slot[1] = 7;
235                 lane_to_slot[2] = 6;
236                 lane_to_slot[3] = 5;
237                 lane_to_slot[6] = 3;
238                 lane_to_slot[7] = 3;
239                 break;
240         case 0xA5:
241                 lane_to_slot[1] = 7;
242                 lane_to_slot[6] = 3;
243                 lane_to_slot[7] = 3;
244                 break;
245         case 0xA7:
246                 lane_to_slot[1] = 7;
247                 lane_to_slot[2] = 6;
248                 lane_to_slot[3] = 5;
249                 lane_to_slot[7] = 7;
250                 break;
251         case 0xAA:
252                 lane_to_slot[1] = 7;
253                 lane_to_slot[6] = 7;
254                 lane_to_slot[7] = 7;
255                 break;
256         case 0x40:
257                 lane_to_slot[2] = 7;
258                 lane_to_slot[3] = 7;
259                 break;
260         default:
261                 printf("qds: Fman: Unsupported SerDes Protocol 0x%02x\n",
262                        serdes1_prtcl);
263                 break;
264         }
265 }
266
267 /*
268  * Given the following ...
269  *
270  * 1) A pointer to an Fman Ethernet node (as identified by the 'compat'
271  * compatible string and 'addr' physical address)
272  *
273  * 2) An Fman port
274  *
275  * ... update the phy-handle property of the Ethernet node to point to the
276  * right PHY. This assumes that we already know the PHY for each port.
277  *
278  * The offset of the Fman Ethernet node is also passed in for convenience, but
279  * it is not used, and we recalculate the offset anyway.
280  *
281  * Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC.
282  * Inside the Fman, "ports" are things that connect to MACs. We only call them
283  * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs
284  * and ports are the same thing.
285  *
286  */
287 void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
288                               enum fm_port port, int offset)
289 {
290         phy_interface_t intf = fm_info_get_enet_if(port);
291         char phy[16];
292
293         /* The RGMII PHY is identified by the MAC connected to it */
294         if (intf == PHY_INTERFACE_MODE_RGMII) {
295                 sprintf(phy, "rgmii_phy%u", port == FM1_DTSEC4 ? 1 : 2);
296                 fdt_set_phy_handle(fdt, compat, addr, phy);
297         }
298
299         /* The SGMII PHY is identified by the MAC connected to it */
300         if (intf == PHY_INTERFACE_MODE_SGMII) {
301                 int lane = serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC1
302                                                  + port);
303                 u8 slot;
304                 if (lane < 0)
305                         return;
306                 slot = lane_to_slot[lane];
307                 if (slot) {
308                         /* Slot housing a SGMII riser card */
309                         sprintf(phy, "phy_s%x_%02x", slot,
310                                 (fm_info_get_phy_address(port - FM1_DTSEC1)-
311                                 CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR + 1));
312                         fdt_set_phy_handle(fdt, compat, addr, phy);
313                 }
314         }
315 }
316
317 void fdt_fixup_board_enet(void *fdt)
318 {
319         int i, lane, idx;
320
321         for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
322                 idx = i - FM1_DTSEC1;
323                 switch (fm_info_get_enet_if(i)) {
324                 case PHY_INTERFACE_MODE_SGMII:
325                         lane = serdes_get_first_lane(FSL_SRDS_1,
326                                                      SGMII_FM1_DTSEC1 + idx);
327                         if (lane < 0)
328                                 break;
329
330                         switch (mdio_mux[i]) {
331                         case EMI1_SLOT3:
332                                 fdt_status_okay_by_alias(fdt, "emi1_slot3");
333                                 break;
334                         case EMI1_SLOT5:
335                                 fdt_status_okay_by_alias(fdt, "emi1_slot5");
336                                 break;
337                         case EMI1_SLOT6:
338                                 fdt_status_okay_by_alias(fdt, "emi1_slot6");
339                                 break;
340                         case EMI1_SLOT7:
341                                 fdt_status_okay_by_alias(fdt, "emi1_slot7");
342                                 break;
343                         }
344                 break;
345                 case PHY_INTERFACE_MODE_RGMII:
346                         if (i == FM1_DTSEC4)
347                                 fdt_status_okay_by_alias(fdt, "emi1_rgmii0");
348
349                         if (i == FM1_DTSEC5)
350                                 fdt_status_okay_by_alias(fdt, "emi1_rgmii1");
351                         break;
352                 default:
353                         break;
354                 }
355         }
356 }
357 #endif /* #ifdef CONFIG_FMAN_ENET */
358
359 static void set_brdcfg9_for_gtx_clk(void)
360 {
361         u8 brdcfg9;
362         brdcfg9 = QIXIS_READ(brdcfg[9]);
363 /* Initializing EPHY2 clock to RGMII mode */
364         brdcfg9 &= ~(BRDCFG9_EPHY2_MASK);
365         brdcfg9 |= (BRDCFG9_EPHY2_VAL);
366         QIXIS_WRITE(brdcfg[9], brdcfg9);
367 }
368
369 void t1040_handle_phy_interface_sgmii(int i)
370 {
371         int lane, idx, slot;
372         idx = i - FM1_DTSEC1;
373         lane = serdes_get_first_lane(FSL_SRDS_1,
374                         SGMII_FM1_DTSEC1 + idx);
375
376         if (lane < 0)
377                 return;
378         slot = lane_to_slot[lane];
379
380         switch (slot) {
381         case 1:
382                 mdio_mux[i] = EMI1_SLOT1;
383                 fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
384                 break;
385         case 3:
386                 if (FM1_DTSEC4 == i)
387                         fm_info_set_phy_address(i, riser_phy_addr[0]);
388                 if (FM1_DTSEC5 == i)
389                         fm_info_set_phy_address(i, riser_phy_addr[1]);
390
391                 mdio_mux[i] = EMI1_SLOT3;
392
393                 fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
394                 break;
395         case 4:
396                 mdio_mux[i] = EMI1_SLOT4;
397                 fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
398                 break;
399         case 5:
400                 /* Slot housing a SGMII riser card? */
401                 fm_info_set_phy_address(i, riser_phy_addr[0]);
402                 mdio_mux[i] = EMI1_SLOT5;
403                 fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
404                 break;
405         case 6:
406                 /* Slot housing a SGMII riser card? */
407                 fm_info_set_phy_address(i, riser_phy_addr[0]);
408                 mdio_mux[i] = EMI1_SLOT6;
409                 fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
410                 break;
411         case 7:
412                 if (FM1_DTSEC1 == i)
413                         fm_info_set_phy_address(i, riser_phy_addr[0]);
414                 if (FM1_DTSEC2 == i)
415                         fm_info_set_phy_address(i, riser_phy_addr[1]);
416                 if (FM1_DTSEC3 == i)
417                         fm_info_set_phy_address(i, riser_phy_addr[2]);
418                 if (FM1_DTSEC5 == i)
419                         fm_info_set_phy_address(i, riser_phy_addr[3]);
420
421                 mdio_mux[i] = EMI1_SLOT7;
422                 fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
423                 break;
424         default:
425                 break;
426         }
427         fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
428 }
429 void t1040_handle_phy_interface_rgmii(int i)
430 {
431         fm_info_set_phy_address(i, i == FM1_DTSEC5 ?
432                         CONFIG_SYS_FM1_DTSEC5_PHY_ADDR :
433                         CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
434         mdio_mux[i] = (i == FM1_DTSEC5) ? EMI1_RGMII1 :
435                 EMI1_RGMII0;
436         fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
437 }
438
439 int board_eth_init(bd_t *bis)
440 {
441 #ifdef CONFIG_FMAN_ENET
442         struct memac_mdio_info memac_mdio_info;
443         unsigned int i;
444 #ifdef CONFIG_VSC9953
445         int lane;
446         int phy_addr;
447         phy_interface_t phy_int;
448         struct mii_dev *bus;
449 #endif
450
451         printf("Initializing Fman\n");
452         set_brdcfg9_for_gtx_clk();
453
454         initialize_lane_to_slot();
455
456         /* Initialize the mdio_mux array so we can recognize empty elements */
457         for (i = 0; i < NUM_FM_PORTS; i++)
458                 mdio_mux[i] = EMI_NONE;
459
460         memac_mdio_info.regs =
461                 (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
462         memac_mdio_info.name = DEFAULT_FM_MDIO_NAME;
463
464         /* Register the real 1G MDIO bus */
465         fm_memac_mdio_init(bis, &memac_mdio_info);
466
467         /* Register the muxing front-ends to the MDIO buses */
468         t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII0);
469         t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
470         t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
471         t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
472         t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
473         t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
474         t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT6);
475         t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7);
476
477         /*
478          * Program on board RGMII PHY addresses. If the SGMII Riser
479          * card used, we'll override the PHY address later. For any DTSEC that
480          * is RGMII, we'll also override its PHY address later. We assume that
481          * DTSEC4 and DTSEC5 are used for RGMII.
482          */
483         fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
484         fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_DTSEC5_PHY_ADDR);
485
486         for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
487                 switch (fm_info_get_enet_if(i)) {
488                 case PHY_INTERFACE_MODE_QSGMII:
489                         fm_info_set_mdio(i, NULL);
490                         break;
491                 case PHY_INTERFACE_MODE_SGMII:
492                         t1040_handle_phy_interface_sgmii(i);
493                         break;
494
495                 case PHY_INTERFACE_MODE_RGMII:
496                         /* Only DTSEC4 and DTSEC5 can be routed to RGMII */
497                         t1040_handle_phy_interface_rgmii(i);
498                         break;
499                 default:
500                         break;
501                 }
502         }
503
504 #ifdef CONFIG_VSC9953
505         for (i = 0; i < VSC9953_MAX_PORTS; i++) {
506                 lane = -1;
507                 phy_addr = 0;
508                 phy_int = PHY_INTERFACE_MODE_NONE;
509                 switch (i) {
510                 case 0:
511                 case 1:
512                 case 2:
513                 case 3:
514                         lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_A);
515                         /* PHYs connected over QSGMII */
516                         if (lane >= 0) {
517                                 phy_addr = CONFIG_SYS_FM1_QSGMII21_PHY_ADDR +
518                                                 i;
519                                 phy_int = PHY_INTERFACE_MODE_QSGMII;
520                                 break;
521                         }
522                         lane = serdes_get_first_lane(FSL_SRDS_1,
523                                         SGMII_SW1_MAC1 + i);
524
525                         if (lane < 0)
526                                 break;
527
528                         /* PHYs connected over QSGMII */
529                         if (i != 3 || lane_to_slot[lane] == 7)
530                                 phy_addr = CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR
531                                         + i;
532                         else
533                                 phy_addr = CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR;
534                         phy_int = PHY_INTERFACE_MODE_SGMII;
535                         break;
536                 case 4:
537                 case 5:
538                 case 6:
539                 case 7:
540                         lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_B);
541                         /* PHYs connected over QSGMII */
542                         if (lane >= 0) {
543                                 phy_addr = CONFIG_SYS_FM1_QSGMII11_PHY_ADDR +
544                                                 i - 4;
545                                 phy_int = PHY_INTERFACE_MODE_QSGMII;
546                                 break;
547                         }
548                         lane = serdes_get_first_lane(FSL_SRDS_1,
549                                         SGMII_SW1_MAC1 + i);
550                         /* PHYs connected over SGMII */
551                         if (lane >= 0) {
552                                 phy_addr = CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR
553                                                 + i - 3;
554                                 phy_int = PHY_INTERFACE_MODE_SGMII;
555                         }
556                         break;
557                 case 8:
558                         if (serdes_get_first_lane(FSL_SRDS_1,
559                                                   SGMII_FM1_DTSEC1) < 0)
560                                 /* FM1@DTSEC1 is connected to SW1@PORT8 */
561                                 vsc9953_port_enable(i);
562                         break;
563                 case 9:
564                         if (serdes_get_first_lane(FSL_SRDS_1,
565                                                   SGMII_FM1_DTSEC2) < 0) {
566                                 /* Enable L2 On MAC2 using SCFG */
567                                 struct ccsr_scfg *scfg = (struct ccsr_scfg *)
568                                                 CONFIG_SYS_MPC85xx_SCFG;
569
570                                 out_be32(&scfg->esgmiiselcr,
571                                          in_be32(&scfg->esgmiiselcr) |
572                                          (0x80000000));
573                                 vsc9953_port_enable(i);
574                         }
575                         break;
576                 }
577
578                 if (lane >= 0) {
579                         bus = mii_dev_for_muxval(lane_to_slot[lane]);
580                         vsc9953_port_info_set_mdio(i, bus);
581                         vsc9953_port_enable(i);
582                 }
583                 vsc9953_port_info_set_phy_address(i, phy_addr);
584                 vsc9953_port_info_set_phy_int(i, phy_int);
585         }
586
587 #endif
588         cpu_eth_init(bis);
589 #endif
590
591         return pci_eth_init(bis);
592 }