3 The T1024/T1023 dual core and T1014/T1013 single core QorIQ communication processor
4 combines two or one 64-bit Power Architecture e5500 core respectively with high
5 performance datapath acceleration logic, and network peripheral bus interfaces
6 required for networking and telecommunications. This processor can be used in
7 applications such as enterprise WLAN access points, routers, switches, firewall
8 and other packet processing intensive small enterprise and branch office appliances,
9 and general-purpose embedded computing. Its high level of integration offers
10 significant performance benefits and greatly helps to simplify board design.
13 The T1024 SoC includes the following function and features:
14 - two e5500 cores, each with a private 256 KB L2 cache
15 - Up to 1.4 GHz with 64-bit ISA support (Power Architecture v2.06-compliant)
16 - Three levels of instructions: User, supervisor, and hypervisor
17 - Independent boot and reset
18 - Secure boot capability
19 - 256 KB shared L3 CoreNet platform cache (CPC)
20 - Interconnect CoreNet platform
21 - CoreNet coherency manager supporting coherent and noncoherent transactions
22 with prioritization and bandwidth allocation amongst CoreNet endpoints
23 - 150 Gbps coherent read bandwidth
24 - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support
25 - Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions:
26 - Packet parsing, classification, and distribution
27 - Queue management for scheduling, packet sequencing, and congestion management
28 - Cryptography Acceleration (SEC 5.x)
30 - Hardware buffer management for buffer allocation and deallocation
31 - MACSEC on DPAA-based Ethernet ports
33 - Four 1 Gbps Ethernet controllers
34 - Parallel Ethernet interfaces
35 - Two RGMII interfaces
36 - High speed peripheral interfaces
37 - Three PCI Express 2.0 controllers/ports running at up to 5 GHz
38 - One SATA controller supporting 1.5 and 3.0 Gb/s operation
39 - One QSGMII interface
40 - Four SGMII interface supporting 1000 Mbps
41 - Three SGMII interfaces supporting up to 2500 Mbps
42 - 10GbE XFI or 10Base-KR interface
43 - Additional peripheral interfaces
44 - Two USB 2.0 controllers with integrated PHY
47 - Four I2C controllers
49 - Four GPIO controllers
50 - Integrated flash controller (IFC)
51 - LCD interface (DIU) with 12 bit dual data rate
52 - Multicore programmable interrupt controller (PIC)
53 - Two 8-channel DMA engines
54 - Single source clocking implementation
55 - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
57 - 32-bit RISC controller for flexible support of the communications peripherals
58 - Serial DMA channel for receive and transmit on all serial channels
59 - Two universal communication controllers, supporting TDM, HDLC, and UART
63 T1023 is a reduced personality of T1024 without QUICC Engine, DIU, and
64 unavailable deep sleep. Rest of the blocks are almost same as T1024.
65 Differences between T1024 and T1023
75 T1024RDB board Overview
76 -----------------------
78 - Two on-board 10M/100M/1G bps RGMII ethernet ports
79 - One on-board 10G bps Base-T port.
81 - Supports 64-bit 4GB DDR3L DIMM
83 - One on-board PCIe slot.
84 - Two on-board PCIe Mini-PCIe connectors.
86 - NOR: 128MB 16-bit NOR Flash
87 - NAND: 1GB 8-bit NAND flash
88 - CPLD: for system controlling with programable header on-board
90 - Supports two USB 2.0 ports with integrated PHYs
91 - Two type A ports with 5V@1.5A per port.
93 - one SD connector supporting 1.8V/3.3V via J53.
95 - On-board 64MB SPI flash
101 Memory map on T1024RDB
102 ----------------------
103 Start Address End Address Description Size
104 0xF_FFDF_0000 0xF_FFDF_0FFF IFC - CPLD 4KB
105 0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB
106 0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB
107 0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB
108 0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB
109 0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB
110 0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB
111 0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB
112 0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB
113 0xF_0000_0000 0xF_003F_FFFF DCSR 4MB
114 0xC_2000_0000 0xC_2FFF_FFFF PCI Express 3 Mem Space 256MB
115 0xC_1000_0000 0xC_1FFF_FFFF PCI Express 2 Mem Space 256MB
116 0xC_0000_0000 0xC_0FFF_FFFF PCI Express 1 Mem Space 256MB
117 0x0_0000_0000 0x0_ffff_ffff DDR 4GB
120 128MB NOR Flash memory Map
121 --------------------------
122 Start Address End Address Definition Max size
123 0xEFF40000 0xEFFFFFFF u-boot (current bank) 768KB
124 0xEFF20000 0xEFF3FFFF u-boot env (current bank) 128KB
125 0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB
126 0xEFE00000 0xEFE3FFFF QE firmware (current bank) 256KB
127 0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB
128 0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB
129 0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB
130 0xEC000000 0xEC01FFFF RCW (alt bank) 128KB
131 0xEBF40000 0xEBFFFFFF u-boot (alt bank) 768KB
132 0xEBF20000 0xEBF3FFFF u-boot env (alt bank) 128KB
133 0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB
134 0xEBE00000 0xEBE3FFFF QE firmware (alt bank) 256KB
135 0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB
136 0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 1MB
137 0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB
138 0xE8000000 0xE801FFFF RCW (current bank) 128KB
141 T1024 Clock frequency
142 ---------------------
143 BIN Core DDR Platform FMan
144 Bin1: 1400MHz 1600MT/s 400MHz 700MHz
145 Bin2: 1200MHz 1600MT/s 400MHz 600MHz
146 Bin3: 1000MHz 1600MT/s 400MHz 500MHz
149 Software configurations and board settings
150 ------------------------------------------
152 a. build NOR boot image
153 $ make T1024RDB_defconfig
155 b. program u-boot.bin image to NOR flash
156 => tftp 1000000 u-boot.bin
157 => pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize
158 set SW1[1:8] = '00010011', SW2[1] = '1', SW3[4] = '0' for NOR boot
160 Switching between default bank0 and alternate bank4 on NOR flash
161 To change boot source to vbank4:
162 via software: run command 'cpld reset altbank' in u-boot.
163 via DIP-switch: set SW3[5:7] = '100'
165 To change boot source to vbank0:
166 via software: run command 'cpld reset' in u-boot.
167 via DIP-Switch: set SW3[5:7] = '000'
170 a. build PBL image for NAND boot
171 $ make T1024RDB_NAND_defconfig
173 b. program u-boot-with-spl-pbl.bin to NAND flash
174 => tftp 1000000 u-boot-with-spl-pbl.bin
175 => nand erase 0 $filesize
176 => nand write 1000000 0 $filesize
177 set SW1[1:8] = '10001000', SW2[1] = '1', SW3[4] = '1' for NAND boot
180 a. build PBL image for SPI boot
181 $ make T1024RDB_SPIFLASH_defconfig
183 b. program u-boot-with-spl-pbl.bin to SPI flash
184 => tftp 1000000 u-boot-with-spl-pbl.bin
187 => sf write 1000000 0 $filesize
188 set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot
191 a. build PBL image for SD boot
192 $ make T1024RDB_SDCARD_defconfig
194 b. program u-boot-with-spl-pbl.bin to SD/MMC card
195 => tftp 1000000 u-boot-with-spl-pbl.bin
196 => mmc write 1000000 8 0x800
197 => tftp 1000000 fsl_fman_ucode_t1024_xx.bin
198 => mmc write 1000000 0x820 80
199 set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot
202 2-stage NAND/SPI/SD boot loader
203 -------------------------------
204 PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM.
205 SPL further initializes DDR using SPD and environment variables
206 and copy u-boot(768 KB) from NAND/SPI/SD device to DDR.
207 Finally SPL transers control to u-boot for futher booting.
209 SPL has following features:
210 - Executes within 256K
211 - No relocation required
213 Run time view of SPL framework
214 -------------------------------------------------
216 -------------------------------------------------
217 |SecureBoot header | 0xFFFC0000 (32KB) |
218 -------------------------------------------------
219 |GD, BD | 0xFFFC8000 (4KB) |
220 -------------------------------------------------
221 |ENV | 0xFFFC9000 (8KB) |
222 -------------------------------------------------
223 |HEAP | 0xFFFCB000 (30KB) |
224 -------------------------------------------------
225 |STACK | 0xFFFD8000 (22KB) |
226 -------------------------------------------------
227 |U-boot SPL | 0xFFFD8000 (160KB) |
228 -------------------------------------------------
230 NAND Flash memory Map on T1024RDB
231 -------------------------------------------------------------
232 Start End Definition Size
233 0x000000 0x0FFFFF u-boot 1MB(2 block)
234 0x100000 0x17FFFF u-boot env 512KB(1 block)
235 0x180000 0x1FFFFF FMAN Ucode 512KB(1 block)
236 0x200000 0x27FFFF QE Firmware 512KB(1 block)
239 SD Card memory Map on T1024RDB
240 ----------------------------------------------------
241 Block #blocks Definition Size
242 0x008 2048 u-boot img 1MB
243 0x800 0016 u-boot env 8KB
244 0x820 0256 FMAN Ucode 128KB
245 0x920 0256 QE Firmware 128KB
248 SPI Flash memory Map on T1024RDB
249 ----------------------------------------------------
250 Start End Definition Size
251 0x000000 0x0FFFFF u-boot img 1MB
252 0x100000 0x101FFF u-boot env 8KB
253 0x110000 0x12FFFF FMAN Ucode 128KB
254 0x130000 0x14FFFF QE Firmware 128KB
257 For more details, please refer to T1024RDB Reference Manual and access
258 website www.freescale.com and Freescale QorIQ SDK Infocenter document.