1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2014 Freescale Semiconductor, Inc.
5 * Shengzhou Liu <Shengzhou.Liu@freescale.com>
10 #include <fdt_support.h>
15 #include <asm/processor.h>
16 #include <asm/immap_85xx.h>
17 #include <asm/fsl_law.h>
18 #include <asm/fsl_serdes.h>
19 #include <asm/fsl_portals.h>
20 #include <asm/fsl_liodn.h>
26 #include <fsl_dtsec.h>
27 #include <asm/fsl_serdes.h>
28 #include "../common/qixis.h"
29 #include "../common/fman.h"
30 #include "t102xqds_qixis.h"
32 #define EMI_NONE 0xFFFFFFFF
42 static int mdio_mux[NUM_FM_PORTS];
44 static const char * const mdio_names[] = {
45 "T1024QDS_MDIO_RGMII1",
46 "T1024QDS_MDIO_RGMII2",
47 "T1024QDS_MDIO_SLOT1",
48 "T1024QDS_MDIO_SLOT2",
49 "T1024QDS_MDIO_SLOT3",
50 "T1024QDS_MDIO_SLOT4",
51 "T1024QDS_MDIO_SLOT5",
56 /* Map SerDes1 4 lanes to default slot, will be initialized dynamically */
57 static u8 lane_to_slot[] = {2, 3, 4, 5};
59 static const char *t1024qds_mdio_name_for_muxval(u8 muxval)
61 return mdio_names[muxval];
64 struct mii_dev *mii_dev_for_muxval(u8 muxval)
72 name = t1024qds_mdio_name_for_muxval(muxval);
75 printf("No bus for muxval %x\n", muxval);
79 bus = miiphy_get_dev_by_name(name);
82 printf("No bus by name %s\n", name);
89 struct t1024qds_mdio {
91 struct mii_dev *realbus;
94 static void t1024qds_mux_mdio(u8 muxval)
99 brdcfg4 = QIXIS_READ(brdcfg[4]);
100 brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
101 brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
102 QIXIS_WRITE(brdcfg[4], brdcfg4);
106 static int t1024qds_mdio_read(struct mii_dev *bus, int addr, int devad,
109 struct t1024qds_mdio *priv = bus->priv;
111 t1024qds_mux_mdio(priv->muxval);
113 return priv->realbus->read(priv->realbus, addr, devad, regnum);
116 static int t1024qds_mdio_write(struct mii_dev *bus, int addr, int devad,
117 int regnum, u16 value)
119 struct t1024qds_mdio *priv = bus->priv;
121 t1024qds_mux_mdio(priv->muxval);
123 return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
126 static int t1024qds_mdio_reset(struct mii_dev *bus)
128 struct t1024qds_mdio *priv = bus->priv;
130 return priv->realbus->reset(priv->realbus);
133 static int t1024qds_mdio_init(char *realbusname, u8 muxval)
135 struct t1024qds_mdio *pmdio;
136 struct mii_dev *bus = mdio_alloc();
139 printf("Failed to allocate t1024qds MDIO bus\n");
143 pmdio = malloc(sizeof(*pmdio));
145 printf("Failed to allocate t1024qds private data\n");
150 bus->read = t1024qds_mdio_read;
151 bus->write = t1024qds_mdio_write;
152 bus->reset = t1024qds_mdio_reset;
153 strcpy(bus->name, t1024qds_mdio_name_for_muxval(muxval));
155 pmdio->realbus = miiphy_get_dev_by_name(realbusname);
157 if (!pmdio->realbus) {
158 printf("No bus with name %s\n", realbusname);
164 pmdio->muxval = muxval;
166 return mdio_register(bus);
169 void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
170 enum fm_port port, int offset)
172 struct fixed_link f_link;
174 if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_RGMII) {
175 if (port == FM1_DTSEC3) {
176 fdt_set_phy_handle(fdt, compat, addr, "rgmii_phy2");
177 fdt_setprop_string(fdt, offset, "phy-connection-type",
179 fdt_status_okay_by_alias(fdt, "emi1_rgmii1");
181 } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
182 if (port == FM1_DTSEC1) {
183 fdt_set_phy_handle(fdt, compat, addr,
184 "sgmii_vsc8234_phy_s5");
185 } else if (port == FM1_DTSEC2) {
186 fdt_set_phy_handle(fdt, compat, addr,
187 "sgmii_vsc8234_phy_s4");
189 } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) {
190 if (port == FM1_DTSEC3) {
191 fdt_set_phy_handle(fdt, compat, addr,
192 "sgmii_aqr105_phy_s3");
194 } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) {
197 fdt_set_phy_handle(fdt, compat, addr, "qsgmii_phy_p1");
200 fdt_set_phy_handle(fdt, compat, addr, "qsgmii_phy_p2");
203 fdt_set_phy_handle(fdt, compat, addr, "qsgmii_phy_p3");
206 fdt_set_phy_handle(fdt, compat, addr, "qsgmii_phy_p4");
211 fdt_delprop(fdt, offset, "phy-connection-type");
212 fdt_setprop_string(fdt, offset, "phy-connection-type",
214 fdt_status_okay_by_alias(fdt, "emi1_slot2");
215 } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) {
217 f_link.phy_id = port;
219 f_link.link_speed = 10000;
221 f_link.asym_pause = 0;
223 fdt_delprop(fdt, offset, "phy-handle");
224 fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));
225 fdt_setprop_string(fdt, offset, "phy-connection-type", "xgmii");
229 void fdt_fixup_board_enet(void *fdt)
234 * This function reads RCW to check if Serdes1{A:D} is configured
235 * to slot 1/2/3/4/5 and update the lane_to_slot[] array accordingly
237 static void initialize_lane_to_slot(void)
239 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
240 u32 srds_s1 = in_be32(&gur->rcwsr[4]) &
241 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
243 srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
255 int board_eth_init(bd_t *bis)
257 #if defined(CONFIG_FMAN_ENET)
258 int i, idx, lane, slot, interface;
259 struct memac_mdio_info dtsec_mdio_info;
260 struct memac_mdio_info tgec_mdio_info;
261 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
264 srds_s1 = in_be32(&gur->rcwsr[4]) &
265 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
266 srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
268 initialize_lane_to_slot();
270 /* Initialize the mdio_mux array so we can recognize empty elements */
271 for (i = 0; i < NUM_FM_PORTS; i++)
272 mdio_mux[i] = EMI_NONE;
274 dtsec_mdio_info.regs =
275 (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
277 dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
279 /* Register the 1G MDIO bus */
280 fm_memac_mdio_init(bis, &dtsec_mdio_info);
282 tgec_mdio_info.regs =
283 (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
284 tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
286 /* Register the 10G MDIO bus */
287 fm_memac_mdio_init(bis, &tgec_mdio_info);
289 /* Register the muxing front-ends to the MDIO buses */
290 t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
291 t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
292 t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
293 t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
294 t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
295 t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
296 t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
297 t1024qds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
299 /* Set the two on-board RGMII PHY address */
300 fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR);
301 fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR);
306 /* QSGMII in Slot2 */
307 fm_info_set_phy_address(FM1_DTSEC1, 0x8);
308 fm_info_set_phy_address(FM1_DTSEC2, 0x9);
309 fm_info_set_phy_address(FM1_DTSEC3, 0xa);
310 fm_info_set_phy_address(FM1_DTSEC4, 0xb);
315 * XFI does not need a PHY to work, but to avoid U-Boot use
316 * default PHY address which is zero to a MAC when it found
317 * a MAC has no PHY address, we give a PHY address to XFI
318 * MAC, and should not use a real XAUI PHY address, since
319 * MDIO can access it successfully, and then MDIO thinks the
320 * XAUI card is used for the XFI MAC, which will cause error.
322 fm_info_set_phy_address(FM1_10GEC1, 4);
323 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
326 /* SGMII in Slot3, Slot4, Slot5 */
327 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_AQ_PHY_ADDR_S5);
328 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_AQ_PHY_ADDR_S4);
329 fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT1_PHY_ADDR);
332 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_AQ_PHY_ADDR_S5);
333 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_AQ_PHY_ADDR_S4);
334 fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_AQ_PHY_ADDR_S3);
337 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
340 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
341 fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_AQ_PHY_ADDR_S3);
344 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
347 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
348 fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT1_PHY_ADDR);
351 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
352 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
355 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
356 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
357 fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT1_PHY_ADDR);
363 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
364 idx = i - FM1_DTSEC1;
365 interface = fm_info_get_enet_if(i);
367 case PHY_INTERFACE_MODE_SGMII:
368 case PHY_INTERFACE_MODE_SGMII_2500:
369 case PHY_INTERFACE_MODE_QSGMII:
370 if (interface == PHY_INTERFACE_MODE_SGMII) {
371 lane = serdes_get_first_lane(FSL_SRDS_1,
372 SGMII_FM1_DTSEC1 + idx);
373 } else if (interface == PHY_INTERFACE_MODE_SGMII_2500) {
374 lane = serdes_get_first_lane(FSL_SRDS_1,
375 SGMII_2500_FM1_DTSEC1 + idx);
377 lane = serdes_get_first_lane(FSL_SRDS_1,
384 slot = lane_to_slot[lane];
385 debug("FM1@DTSEC%u expects SGMII in slot %u\n",
387 if (QIXIS_READ(present2) & (1 << (slot - 1)))
392 mdio_mux[i] = EMI1_SLOT2;
393 fm_info_set_mdio(i, mii_dev_for_muxval(
397 mdio_mux[i] = EMI1_SLOT3;
398 fm_info_set_mdio(i, mii_dev_for_muxval(
402 mdio_mux[i] = EMI1_SLOT4;
403 fm_info_set_mdio(i, mii_dev_for_muxval(
407 mdio_mux[i] = EMI1_SLOT5;
408 fm_info_set_mdio(i, mii_dev_for_muxval(
413 case PHY_INTERFACE_MODE_RGMII:
415 mdio_mux[i] = EMI1_RGMII2;
416 else if (i == FM1_DTSEC4)
417 mdio_mux[i] = EMI1_RGMII1;
418 fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
425 for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
426 idx = i - FM1_10GEC1;
427 switch (fm_info_get_enet_if(i)) {
428 case PHY_INTERFACE_MODE_XGMII:
429 lane = serdes_get_first_lane(FSL_SRDS_1,
434 fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
442 #endif /* CONFIG_FMAN_ENET */
444 return pci_eth_init(bis);