2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
11 #include <fsl_ddr_sdram.h>
12 #include <fsl_ddr_dimm_params.h>
13 #include <asm/fsl_law.h>
15 DECLARE_GLOBAL_DATA_PTR;
17 struct board_specific_parameters {
19 u32 datarate_mhz_high;
28 * datarate_mhz_high values need to be in ascending order
30 static const struct board_specific_parameters udimm0[] = {
33 * num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
34 * ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
36 #if defined(CONFIG_SYS_FSL_DDR4)
37 {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},
38 {2, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,},
39 {1, 1666, 0, 4, 6, 0x0708090B, 0x0C0D0E09,},
40 {1, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,},
41 {1, 2200, 0, 4, 7, 0x08090A0D, 0x0F0F100C,},
42 #elif defined(CONFIG_SYS_FSL_DDR3)
43 {2, 833, 0, 4, 6, 0x06060607, 0x08080807,},
44 {2, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,},
45 {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},
46 {1, 833, 0, 4, 6, 0x06060607, 0x08080807,},
47 {1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,},
48 {1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},
50 #error DDR type not defined
55 static const struct board_specific_parameters *udimms[] = {
59 void fsl_ddr_board_options(memctl_options_t *popts,
61 unsigned int ctrl_num)
63 const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
65 struct cpu_type *cpu = gd->arch.cpu;
68 printf("Not supported controller number %d\n", ctrl_num);
76 /* Get clk_adjust according to the board ddr freqency and n_banks
77 * specified in board_specific_parameters table.
79 ddr_freq = get_ddr_freq(0) / 1000000;
80 while (pbsp->datarate_mhz_high) {
81 if (pbsp->n_ranks == pdimm->n_ranks &&
82 (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
83 if (ddr_freq <= pbsp->datarate_mhz_high) {
84 popts->clk_adjust = pbsp->clk_adjust;
85 popts->wrlvl_start = pbsp->wrlvl_start;
86 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
87 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
96 printf("Error: board specific timing not found\n");
97 printf("for data rate %lu MT/s\n", ddr_freq);
98 printf("Trying to use the highest speed (%u) parameters\n",
99 pbsp_highest->datarate_mhz_high);
100 popts->clk_adjust = pbsp_highest->clk_adjust;
101 popts->wrlvl_start = pbsp_highest->wrlvl_start;
102 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
103 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
105 panic("DIMM is not supported by this board");
108 debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
109 pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
110 debug("\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, ",
111 pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2);
112 debug("wrlvl_ctrl_3 0x%x\n", pbsp->wrlvl_ctl_3);
115 * Factors to consider for half-strength driver enable:
116 * - number of DIMMs installed
118 popts->half_strength_driver_enable = 1;
120 * Write leveling override
122 popts->wrlvl_override = 1;
123 popts->wrlvl_sample = 0xf;
126 * rtt and rtt_wr override
128 popts->rtt_override = 0;
130 /* Enable ZQ calibration */
133 /* DHC_EN =1, ODT = 75 Ohm */
134 #ifdef CONFIG_SYS_FSL_DDR4
135 popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
136 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
137 DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */
139 popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
140 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
143 /* T1023 supports max DDR bus 32bit width, T1024 supports DDR 64bit,
144 * set DDR bus width to 32bit for T1023
146 if (cpu->soc_ver == SVR_T1023)
147 popts->data_bus_width = DDR_DATA_BUS_WIDTH_32;
149 #ifdef CONFIG_FORCE_DDR_DATA_BUS_WIDTH_32
150 /* for DDR bus 32bit test on T1024 */
151 popts->data_bus_width = DDR_DATA_BUS_WIDTH_32;
155 phys_size_t initdram(int board_type)
157 phys_size_t dram_size;
159 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
160 puts("Initializing....using SPD\n");
162 dram_size = fsl_ddr_sdram();
163 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
164 dram_size *= 0x100000;
166 /* DDR has been initialised by first stage boot loader */
167 dram_size = fsl_ddr_sdram_size();