2 * Copyright 2011 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <linux/compiler.h>
28 #include <asm/processor.h>
29 #include <asm/cache.h>
30 #include <asm/immap_85xx.h>
31 #include <asm/fsl_law.h>
32 #include <asm/fsl_serdes.h>
33 #include <asm/fsl_portals.h>
34 #include <asm/fsl_liodn.h>
36 #include <configs/P3060QDS.h>
38 #include <fdt_support.h>
40 #include "../common/qixis.h"
42 #include "p3060qds_qixis.h"
44 DECLARE_GLOBAL_DATA_PTR;
49 struct cpu_type *cpu = gd->cpu;
50 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
53 printf("Board: %s", cpu->name);
56 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
57 QIXIS_READ(id), QIXIS_READ(arch), QIXIS_READ(scver));
59 sw = QIXIS_READ(brdcfg[0]);
60 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
63 printf("vBank: %d\n", sw);
69 printf("invalid setting of SW%u\n", PIXIS_LBMAP_SWITCH);
71 puts("Reset Configuration Word (RCW):");
72 for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
73 u32 rcw = in_be32(&gur->rcwsr[i]);
76 printf("\n %08x:", i * 4);
81 puts("SERDES Reference Clocks: ");
82 sw = QIXIS_READ(brdcfg[2]);
83 for (i = 0; i < 3; i++) {
84 static const char * const freq[] = {"100", "125", "Reserved",
86 unsigned int clock = (sw >> (2 * i)) & 3;
88 printf("Bank%u=%sMhz ", i+1, freq[clock]);
95 int board_early_init_f(void)
97 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
99 /* only single DDR controller on QDS board, disable DDR1_MCK4/5 */
100 setbits_be32(&gur->ddrclkdr, 0x00030000);
105 void board_config_serdes_mux(void)
107 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
108 int cfg = (in_be32(&gur->rcwsr[4]) &
109 FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
114 /* set Lane I,J as SGMII */
115 QIXIS_WRITE(brdcfg[6], BRDCFG6_SD4MX_B | BRDCFG6_SD3MX_A |
116 BRDCFG6_SD2MX_B | BRDCFG6_SD1MX_A);
121 /* set Lane I,J as Aurora Debug */
122 QIXIS_WRITE(brdcfg[6], BRDCFG6_SD4MX_A | BRDCFG6_SD3MX_B |
123 BRDCFG6_SD2MX_A | BRDCFG6_SD1MX_B);
126 puts("Invalid SerDes protocol for P3060QDS\n");
131 void board_config_usb_mux(void)
133 u8 brdcfg4, brdcfg5, brdcfg7;
134 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
135 u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
136 u32 ec1 = rcwsr11 & FSL_CORENET_RCWSR11_EC1;
137 u32 ec2 = rcwsr11 & FSL_CORENET_RCWSR11_EC2;
139 brdcfg4 = QIXIS_READ(brdcfg[4]);
140 brdcfg4 &= ~BRDCFG4_EC_MODE_MASK;
141 if ((ec1 == FSL_CORENET_RCWSR11_EC1_FM1_USB1) &&
142 (ec2 == FSL_CORENET_RCWSR11_EC2_USB2)) {
143 brdcfg4 |= BRDCFG4_EC2_USB_EC1_USB;
145 } else if ((ec1 == FSL_CORENET_RCWSR11_EC1_FM1_USB1) &&
146 ((ec2 == FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2) ||
147 (ec2 == FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1))) {
148 brdcfg4 |= BRDCFG4_EC2_RGMII_EC1_USB;
150 } else if ((ec1 == FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1) &&
151 (ec2 == FSL_CORENET_RCWSR11_EC2_USB2)) {
152 brdcfg4 |= BRDCFG4_EC2_USB_EC1_RGMII;
154 } else if ((ec1 == FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1) &&
155 ((ec2 == FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2) ||
156 (ec2 == FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1))) {
157 brdcfg4 |= BRDCFG4_EC2_RGMII_EC1_RGMII;
159 brdcfg4 |= BRDCFG4_EC2_MII_EC1_MII;
161 QIXIS_WRITE(brdcfg[4], brdcfg4);
163 brdcfg5 = QIXIS_READ(brdcfg[5]);
164 brdcfg5 &= ~(BRDCFG5_USB1ID_MASK | BRDCFG5_USB2ID_MASK);
165 brdcfg5 |= (BRDCFG5_USB1ID_CTRL | BRDCFG5_USB2ID_CTRL);
166 QIXIS_WRITE(brdcfg[5], brdcfg5);
168 brdcfg7 = BRDCFG7_JTAGMX_COP_JTAG | BRDCFG7_IQ1MX_IRQ_EVT |
169 BRDCFG7_G1MX_USB1 | BRDCFG7_D1MX_TSEC3USB | BRDCFG7_I3MX_USB1;
170 QIXIS_WRITE(brdcfg[7], brdcfg7);
173 int board_early_init_r(void)
175 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
176 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
179 * Remap Boot flash + PROMJET region to caching-inhibited
180 * so that flash can be erased properly.
183 /* Flush d-cache and invalidate i-cache of any FLASH data */
187 /* invalidate existing TLB entry for flash + promjet */
188 disable_tlb(flash_esel);
190 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
191 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
192 0, flash_esel, BOOKE_PAGESZ_256M, 1);
195 #ifdef CONFIG_SYS_DPAA_QBMAN
198 board_config_serdes_mux();
199 board_config_usb_mux();
204 static const char *serdes_clock_to_string(u32 clock)
207 case SRDS_PLLCR0_RFCK_SEL_100:
209 case SRDS_PLLCR0_RFCK_SEL_125:
211 case SRDS_PLLCR0_RFCK_SEL_156_25:
218 #define NUM_SRDS_BANKS 3
220 int misc_init_r(void)
222 serdes_corenet_t *srds_regs;
223 u32 actual[NUM_SRDS_BANKS];
227 sw = QIXIS_READ(brdcfg[2]);
228 for (i = 0; i < 3; i++) {
229 unsigned int clock = (sw >> (2 * i)) & 3;
232 actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
235 actual[i] = SRDS_PLLCR0_RFCK_SEL_125;
238 actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25;
241 printf("Warning: SDREFCLK%u switch setting of '10' is "
242 "unsupported\n", i + 1);
247 srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
248 for (i = 0; i < NUM_SRDS_BANKS; i++) {
249 u32 pllcr0 = in_be32(&srds_regs->bank[i].pllcr0);
250 u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
251 if (expected != actual[i]) {
252 printf("Warning: SERDES bank %u expects reference clock"
253 " %sMHz, but actual is %sMHz\n", i + 1,
254 serdes_clock_to_string(expected),
255 serdes_clock_to_string(actual[i]));
263 * This is map of CVDD values. 33 means CVDD is 3.3v, 25 means CVDD is 2.5v,
264 * 18 means CVDD is 1.8v.
266 static u8 IO_VSEL[] = {
267 33, 33, 33, 25, 25, 25, 18, 18, 18,
268 33, 33, 33, 25, 25, 25, 18, 18, 18,
269 33, 33, 33, 25, 25, 25, 18, 18, 18,
273 #define IO_VSEL_MASK 0x1f
276 * different CVDD selects diffenert spi flashs, read dutcfg[3] to get CVDD,
277 * then set status of spi flash nodes to 'disabled' according to CVDD.
278 * CVDD '33' will select spi flash0 and flash1, CVDD '25' will select spi
279 * flash2, CVDD '18' will select spi flash3.
281 void fdt_fixup_board_spi(void *blob)
283 u8 sw5 = QIXIS_READ(dutcfg[3]);
285 switch (IO_VSEL[sw5 & IO_VSEL_MASK]) {
288 do_fixup_by_compat(blob, "atmel,at45db081d", "status",
289 "disabled", strlen("disabled") + 1, 1);
290 do_fixup_by_compat(blob, "spansion,sst25wf040", "status",
291 "disabled", strlen("disabled") + 1, 1);
295 do_fixup_by_compat(blob, "spansion,s25sl12801", "status",
296 "disabled", strlen("disabled") + 1, 1);
297 do_fixup_by_compat(blob, "spansion,en25q32", "status",
298 "disabled", strlen("disabled") + 1, 1);
299 do_fixup_by_compat(blob, "spansion,sst25wf040", "status",
300 "disabled", strlen("disabled") + 1, 1);
304 do_fixup_by_compat(blob, "spansion,s25sl12801", "status",
305 "disabled", strlen("disabled") + 1, 1);
306 do_fixup_by_compat(blob, "spansion,en25q32", "status",
307 "disabled", strlen("disabled") + 1, 1);
308 do_fixup_by_compat(blob, "atmel,at45db081d", "status",
309 "disabled", strlen("disabled") + 1, 1);
314 void ft_board_setup(void *blob, bd_t *bd)
319 ft_cpu_setup(blob, bd);
321 base = getenv_bootm_low();
322 size = getenv_bootm_size();
324 fdt_fixup_memory(blob, (u64)base, (u64)size);
327 pci_of_setup(blob, bd);
330 fdt_fixup_liodn(blob);
331 fdt_fixup_dr_usb(blob, bd);
332 fdt_fixup_board_spi(blob);
334 #ifdef CONFIG_SYS_DPAA_FMAN
335 fdt_fixup_fman_ethernet(blob);
336 fdt_fixup_board_enet(blob);