board/freescale/p2041rdb/ddr.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright 2011 Freescale Semiconductor, Inc.
   4  */
   5
   6 #include <common.h>
   7 #include <i2c.h>
   8 #include <hwconfig.h>
   9 #include <init.h>
  10 #include <log.h>
  11 #include <asm/mmu.h>
  12 #include <fsl_ddr_sdram.h>
  13 #include <fsl_ddr_dimm_params.h>
  14 #include <asm/fsl_law.h>
  15
  16 DECLARE_GLOBAL_DATA_PTR;
  17
  18 struct board_specific_parameters {
  19         u32 n_ranks;
  20         u32 datarate_mhz_high;
  21         u32 clk_adjust;
  22         u32 wrlvl_start;
  23         u32 cpo;
  24         u32 write_data_delay;
  25         u32 force_2t;
  26 };
  27
  28 /*
  29  * This table contains all valid speeds we want to override with board
  30  * specific parameters. datarate_mhz_high values need to be in ascending order
  31  * for each n_ranks group.
  32  *
  33  * ranges for parameters:
  34  *  wr_data_delay = 0-6
  35  *  clk adjust = 0-8
  36  *  cpo 2-0x1E (30)
  37  */
  38 static const struct board_specific_parameters dimm0[] = {
  39         /*
  40          * memory controller 0
  41          *   num|  hi|  clk| wrlvl | cpo  |wrdata|2T
  42          * ranks| mhz|adjst| start | delay|
  43          */
  44         {2,   750,    3,     5,   0xff,    2,  0},
  45         {2,  1250,    4,     6,   0xff,    2,  0},
  46         {2,  1350,    5,     7,   0xff,    2,  0},
  47         {2,  1666,    5,     8,   0xff,    2,  0},
  48         {}
  49 };
  50
  51 void fsl_ddr_board_options(memctl_options_t *popts,
  52                                 dimm_params_t *pdimm,
  53                                 unsigned int ctrl_num)
  54 {
  55         const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
  56         ulong ddr_freq;
  57
  58         if (ctrl_num) {
  59                 printf("Wrong parameter for controller number %d", ctrl_num);
  60                 return;
  61         }
  62         if (!pdimm->n_ranks)
  63                 return;
  64
  65         pbsp = dimm0;
  66
  67         /*
  68          * Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
  69          * freqency and n_banks specified in board_specific_parameters table.
  70          */
  71         ddr_freq = get_ddr_freq(0) / 1000000;
  72         while (pbsp->datarate_mhz_high) {
  73                 if (pbsp->n_ranks == pdimm->n_ranks) {
  74                         if (ddr_freq <= pbsp->datarate_mhz_high) {
  75                                 popts->cpo_override = pbsp->cpo;
  76                                 popts->write_data_delay =
  77                                         pbsp->write_data_delay;
  78                                 popts->clk_adjust = pbsp->clk_adjust;
  79                                 popts->wrlvl_start = pbsp->wrlvl_start;
  80                                 popts->twot_en = pbsp->force_2t;
  81                                 goto found;
  82                         }
  83                         pbsp_highest = pbsp;
  84                 }
  85                 pbsp++;
  86         }
  87
  88         if (pbsp_highest) {
  89                 printf("Error: board specific timing not found "
  90                         "for data rate %lu MT/s!\n"
  91                         "Trying to use the highest speed (%u) parameters\n",
  92                         ddr_freq, pbsp_highest->datarate_mhz_high);
  93                 popts->cpo_override = pbsp_highest->cpo;
  94                 popts->write_data_delay = pbsp_highest->write_data_delay;
  95                 popts->clk_adjust = pbsp_highest->clk_adjust;
  96                 popts->wrlvl_start = pbsp_highest->wrlvl_start;
  97                 popts->twot_en = pbsp_highest->force_2t;
  98         } else {
  99                 panic("DIMM is not supported by this board");
 100         }
 101
 102 found:
 103         /*
 104          * Factors to consider for half-strength driver enable:
 105          *      - number of DIMMs installed
 106          */
 107         popts->half_strength_driver_enable = 0;
 108         /* Write leveling override */
 109         popts->wrlvl_override = 1;
 110         popts->wrlvl_sample = 0xf;
 111
 112         /* Rtt and Rtt_WR override */
 113         popts->rtt_override = 0;
 114
 115         /* Enable ZQ calibration */
 116         popts->zq_en = 1;
 117
 118         /* DHC_EN =1, ODT = 60 Ohm */
 119         popts->ddr_cdr1 = DDR_CDR1_DHC_EN;
 120 }
 121
 122 int dram_init(void)
 123 {
 124         phys_size_t dram_size = 0;
 125
 126         puts("Initializing....");
 127
 128         if (fsl_use_spd()) {
 129                 puts("using SPD\n");
 130                 dram_size = fsl_ddr_sdram();
 131         } else {
 132                 puts("no SPD and fixed parameters\n");
 133                 return -ENXIO;
 134         }
 135
 136         dram_size = setup_ddr_tlbs(dram_size / 0x100000);
 137         dram_size *= 0x100000;
 138
 139         debug("    DDR: ");
 140         gd->ram_size = dram_size;
 141
 142         return 0;
 143 }