board_f: Drop return value from initdram()
[oweals/u-boot.git] / board / freescale / p2041rdb / ddr.c
1 /*
2  * Copyright 2011 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:     GPL-2.0
5  */
6
7 #include <common.h>
8 #include <i2c.h>
9 #include <hwconfig.h>
10 #include <asm/mmu.h>
11 #include <fsl_ddr_sdram.h>
12 #include <fsl_ddr_dimm_params.h>
13 #include <asm/fsl_law.h>
14
15 DECLARE_GLOBAL_DATA_PTR;
16
17 struct board_specific_parameters {
18         u32 n_ranks;
19         u32 datarate_mhz_high;
20         u32 clk_adjust;
21         u32 wrlvl_start;
22         u32 cpo;
23         u32 write_data_delay;
24         u32 force_2t;
25 };
26
27 /*
28  * This table contains all valid speeds we want to override with board
29  * specific parameters. datarate_mhz_high values need to be in ascending order
30  * for each n_ranks group.
31  *
32  * ranges for parameters:
33  *  wr_data_delay = 0-6
34  *  clk adjust = 0-8
35  *  cpo 2-0x1E (30)
36  */
37 static const struct board_specific_parameters dimm0[] = {
38         /*
39          * memory controller 0
40          *   num|  hi|  clk| wrlvl | cpo  |wrdata|2T
41          * ranks| mhz|adjst| start | delay|
42          */
43         {2,   750,    3,     5,   0xff,    2,  0},
44         {2,  1250,    4,     6,   0xff,    2,  0},
45         {2,  1350,    5,     7,   0xff,    2,  0},
46         {2,  1666,    5,     8,   0xff,    2,  0},
47         {}
48 };
49
50 void fsl_ddr_board_options(memctl_options_t *popts,
51                                 dimm_params_t *pdimm,
52                                 unsigned int ctrl_num)
53 {
54         const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
55         ulong ddr_freq;
56
57         if (ctrl_num) {
58                 printf("Wrong parameter for controller number %d", ctrl_num);
59                 return;
60         }
61         if (!pdimm->n_ranks)
62                 return;
63
64         pbsp = dimm0;
65
66         /*
67          * Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
68          * freqency and n_banks specified in board_specific_parameters table.
69          */
70         ddr_freq = get_ddr_freq(0) / 1000000;
71         while (pbsp->datarate_mhz_high) {
72                 if (pbsp->n_ranks == pdimm->n_ranks) {
73                         if (ddr_freq <= pbsp->datarate_mhz_high) {
74                                 popts->cpo_override = pbsp->cpo;
75                                 popts->write_data_delay =
76                                         pbsp->write_data_delay;
77                                 popts->clk_adjust = pbsp->clk_adjust;
78                                 popts->wrlvl_start = pbsp->wrlvl_start;
79                                 popts->twot_en = pbsp->force_2t;
80                                 goto found;
81                         }
82                         pbsp_highest = pbsp;
83                 }
84                 pbsp++;
85         }
86
87         if (pbsp_highest) {
88                 printf("Error: board specific timing not found "
89                         "for data rate %lu MT/s!\n"
90                         "Trying to use the highest speed (%u) parameters\n",
91                         ddr_freq, pbsp_highest->datarate_mhz_high);
92                 popts->cpo_override = pbsp_highest->cpo;
93                 popts->write_data_delay = pbsp_highest->write_data_delay;
94                 popts->clk_adjust = pbsp_highest->clk_adjust;
95                 popts->wrlvl_start = pbsp_highest->wrlvl_start;
96                 popts->twot_en = pbsp_highest->force_2t;
97         } else {
98                 panic("DIMM is not supported by this board");
99         }
100
101 found:
102         /*
103          * Factors to consider for half-strength driver enable:
104          *      - number of DIMMs installed
105          */
106         popts->half_strength_driver_enable = 0;
107         /* Write leveling override */
108         popts->wrlvl_override = 1;
109         popts->wrlvl_sample = 0xf;
110
111         /* Rtt and Rtt_WR override */
112         popts->rtt_override = 0;
113
114         /* Enable ZQ calibration */
115         popts->zq_en = 1;
116
117         /* DHC_EN =1, ODT = 60 Ohm */
118         popts->ddr_cdr1 = DDR_CDR1_DHC_EN;
119 }
120
121 int initdram(void)
122 {
123         phys_size_t dram_size = 0;
124
125         puts("Initializing....");
126
127         if (fsl_use_spd()) {
128                 puts("using SPD\n");
129                 dram_size = fsl_ddr_sdram();
130         } else {
131                 puts("no SPD and fixed parameters\n");
132                 return -ENXIO;
133         }
134
135         dram_size = setup_ddr_tlbs(dram_size / 0x100000);
136         dram_size *= 0x100000;
137
138         debug("    DDR: ");
139         gd->ram_size = dram_size;
140
141         return 0;
142 }