board/freescale/p2020ds/p2020ds.c

   1 /*
   2  * Copyright 2007-2009 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <command.h>
  25 #include <pci.h>
  26 #include <asm/processor.h>
  27 #include <asm/mmu.h>
  28 #include <asm/cache.h>
  29 #include <asm/immap_85xx.h>
  30 #include <asm/fsl_pci.h>
  31 #include <asm/fsl_ddr_sdram.h>
  32 #include <asm/io.h>
  33 #include <miiphy.h>
  34 #include <libfdt.h>
  35 #include <fdt_support.h>
  36 #include <tsec.h>
  37 #include <asm/fsl_law.h>
  38 #include <asm/mp.h>
  39 #include <netdev.h>
  40
  41 #include "../common/pixis.h"
  42 #include "../common/sgmii_riser.h"
  43
  44 DECLARE_GLOBAL_DATA_PTR;
  45
  46 phys_size_t fixed_sdram(void);
  47
  48 int checkboard(void)
  49 {
  50         u8 sw7;
  51         u8 *pixis_base = (u8 *)PIXIS_BASE;
  52
  53         puts("Board: P2020DS ");
  54 #ifdef CONFIG_PHYS_64BIT
  55         puts("(36-bit addrmap) ");
  56 #endif
  57
  58         printf("Sys ID: 0x%02x, "
  59                 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
  60                 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
  61                 in_8(pixis_base + PIXIS_PVER));
  62
  63         sw7 = in_8(pixis_base + PIXIS_SW(7));
  64         switch ((sw7 & PIXIS_SW7_LBMAP) >> 6) {
  65                 case 0:
  66                 case 1:
  67                         printf ("vBank: %d\n", ((sw7 & PIXIS_SW7_VBANK) >> 4));
  68                         break;
  69                 case 2:
  70                 case 3:
  71                         puts ("Promjet\n");
  72                         break;
  73         }
  74
  75         return 0;
  76 }
  77
  78 phys_size_t initdram(int board_type)
  79 {
  80         phys_size_t dram_size = 0;
  81
  82         puts("Initializing....");
  83
  84 #ifdef CONFIG_SPD_EEPROM
  85         dram_size = fsl_ddr_sdram();
  86 #else
  87         dram_size = fixed_sdram();
  88
  89         if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
  90                          dram_size,
  91                          LAW_TRGT_IF_DDR) < 0) {
  92                 printf("ERROR setting Local Access Windows for DDR\n");
  93                 return 0;
  94         };
  95 #endif
  96         dram_size = setup_ddr_tlbs(dram_size / 0x100000);
  97         dram_size *= 0x100000;
  98
  99         puts("    DDR: ");
 100         return dram_size;
 101 }
 102
 103 #if !defined(CONFIG_SPD_EEPROM)
 104 /*
 105  * Fixed sdram init -- doesn't use serial presence detect.
 106  */
 107
 108 phys_size_t fixed_sdram(void)
 109 {
 110         volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
 111         uint d_init;
 112
 113         ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
 114         ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
 115         ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
 116         ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
 117         ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
 118         ddr->sdram_md_cntl = CONFIG_SYS_DDR_MODE_CTRL;
 119         ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
 120         ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
 121         ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
 122         ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
 123         ddr->ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL;
 124         ddr->ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL;
 125         ddr->ddr_cdr1 = CONFIG_SYS_DDR_CDR1;
 126         ddr->timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4;
 127         ddr->timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5;
 128
 129         if (!strcmp("performance", getenv("perf_mode"))) {
 130                 /* Performance Mode Values */
 131
 132                 ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG_PERF;
 133                 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS_PERF;
 134                 ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS_PERF;
 135                 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_PERF;
 136                 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_PERF;
 137
 138                 asm("sync;isync");
 139
 140                 udelay(500);
 141
 142                 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL_PERF;
 143         } else {
 144                 /* Stable Mode Values */
 145
 146                 ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG;
 147                 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
 148                 ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS;
 149                 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
 150                 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
 151
 152                 /* ECC will be assumed in stable mode */
 153                 ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
 154                 ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
 155                 ddr->err_sbe = CONFIG_SYS_DDR_SBE;
 156
 157                 asm("sync;isync");
 158
 159                 udelay(500);
 160
 161                 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
 162         }
 163
 164 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 165         d_init = 1;
 166         debug("DDR - 1st controller: memory initializing\n");
 167         /*
 168          * Poll until memory is initialized.
 169          * 512 Meg at 400 might hit this 200 times or so.
 170          */
 171         while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0)
 172                 udelay(1000);
 173         debug("DDR: memory initialized\n\n");
 174         asm("sync; isync");
 175         udelay(500);
 176 #endif
 177
 178         return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 179 }
 180
 181 #endif
 182
 183 #ifdef CONFIG_PCIE1
 184 static struct pci_controller pcie1_hose;
 185 #endif
 186
 187 #ifdef CONFIG_PCIE2
 188 static struct pci_controller pcie2_hose;
 189 #endif
 190
 191 #ifdef CONFIG_PCIE3
 192 static struct pci_controller pcie3_hose;
 193 #endif
 194
 195 int first_free_busno = 0;
 196
 197 #ifdef CONFIG_PCI
 198 void pci_init_board(void)
 199 {
 200         volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 201         uint devdisr = gur->devdisr;
 202         uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
 203         uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
 204
 205         volatile ccsr_fsl_pci_t *pci;
 206         struct pci_controller *hose;
 207         int pcie_ep, pcie_configured;
 208         struct pci_region *r;
 209 /*              u32 temp32; */
 210
 211         debug("   pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
 212                         devdisr, io_sel, host_agent);
 213
 214         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
 215                 printf("    eTSEC2 is in sgmii mode.\n");
 216         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
 217                 printf("    eTSEC3 is in sgmii mode.\n");
 218
 219 #ifdef CONFIG_PCIE2
 220         pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
 221         hose = &pcie2_hose;
 222         pcie_ep = (host_agent == 2) || (host_agent == 4) ||
 223                   (host_agent == 6) || (host_agent == 0);
 224         pcie_configured = (io_sel == 0x2) || (io_sel == 0xe);
 225         r = hose->regions;
 226
 227         if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)) {
 228                 printf("\n    PCIE2 connected to ULI as %s (base addr %x)",
 229                                 pcie_ep ? "End Point" : "Root Complex",
 230                                 (uint)pci);
 231                 if (pci->pme_msg_det) {
 232                         pci->pme_msg_det = 0xffffffff;
 233                         debug(" with errors.  Clearing.  Now 0x%08x",
 234                                 pci->pme_msg_det);
 235                 }
 236                 printf("\n");
 237
 238                 /* inbound */
 239                 r += fsl_pci_setup_inbound_windows(r);
 240
 241                 /* outbound memory */
 242                 pci_set_region(r++,
 243                                 CONFIG_SYS_PCIE2_MEM_BUS,
 244                                 CONFIG_SYS_PCIE2_MEM_PHYS,
 245                                 CONFIG_SYS_PCIE2_MEM_SIZE,
 246                                 PCI_REGION_MEM);
 247
 248                 /* outbound io */
 249                 pci_set_region(r++,
 250                                 CONFIG_SYS_PCIE2_IO_BUS,
 251                                 CONFIG_SYS_PCIE2_IO_PHYS,
 252                                 CONFIG_SYS_PCIE2_IO_SIZE,
 253                                 PCI_REGION_IO);
 254
 255                 hose->region_count = r - hose->regions;
 256                 hose->first_busno = first_free_busno;
 257
 258                 fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
 259                 first_free_busno = hose->last_busno+1;
 260                 printf("    PCIE2 on bus %02x - %02x\n",
 261                         hose->first_busno, hose->last_busno);
 262
 263                 /*
 264                  * The workaround doesn't work on p2020 because the location
 265                  * we try and read isn't valid on p2020, fix this later
 266                  */
 267 #if 0
 268                 /*
 269                  * Activate ULI1575 legacy chip by performing a fake
 270                  * memory access.  Needed to make ULI RTC work.
 271                  * Device 1d has the first on-board memory BAR.
 272                  */
 273
 274                 pci_hose_read_config_dword(hose, PCI_BDF(2, 0x1d, 0),
 275                                 PCI_BASE_ADDRESS_1, &temp32);
 276                 if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) {
 277                         void *p = pci_mem_to_virt(PCI_BDF(2, 0x1d, 0),
 278                                                         temp32, 4, 0);
 279                         debug(" uli1575 read to %p\n", p);
 280                         in_be32(p);
 281                 }
 282 #endif
 283         } else {
 284                 printf("    PCIE2: disabled\n");
 285         }
 286 #else
 287         gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
 288 #endif
 289
 290 #ifdef CONFIG_PCIE3
 291         pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
 292         hose = &pcie3_hose;
 293         pcie_ep = (host_agent == 0) || (host_agent == 3) ||
 294                 (host_agent == 5) || (host_agent == 6);
 295         pcie_configured = (io_sel == 0x2) || (io_sel == 0x4);
 296         r = hose->regions;
 297
 298         if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)) {
 299                 printf("\n    PCIE3 connected to Slot 1 as %s (base addr %x)",
 300                                 pcie_ep ? "End Point" : "Root Complex",
 301                                 (uint)pci);
 302                 if (pci->pme_msg_det) {
 303                         pci->pme_msg_det = 0xffffffff;
 304                         debug(" with errors.  Clearing.  Now 0x%08x",
 305                                 pci->pme_msg_det);
 306                 }
 307                 printf("\n");
 308
 309                 /* inbound */
 310                 r += fsl_pci_setup_inbound_windows(r);
 311
 312                 /* outbound memory */
 313                 pci_set_region(r++,
 314                                 CONFIG_SYS_PCIE3_MEM_BUS,
 315                                 CONFIG_SYS_PCIE3_MEM_PHYS,
 316                                 CONFIG_SYS_PCIE3_MEM_SIZE,
 317                                 PCI_REGION_MEM);
 318
 319                 /* outbound io */
 320                 pci_set_region(r++,
 321                                 CONFIG_SYS_PCIE3_IO_BUS,
 322                                 CONFIG_SYS_PCIE3_IO_PHYS,
 323                                 CONFIG_SYS_PCIE3_IO_SIZE,
 324                                 PCI_REGION_IO);
 325
 326                 hose->region_count = r - hose->regions;
 327                 hose->first_busno = first_free_busno;
 328
 329                 fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
 330
 331                 first_free_busno = hose->last_busno+1;
 332                 printf("    PCIE3 on bus %02x - %02x\n",
 333                                 hose->first_busno, hose->last_busno);
 334
 335         } else {
 336                 printf("    PCIE3: disabled\n");
 337         }
 338 #else
 339         gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */
 340 #endif
 341
 342 #ifdef CONFIG_PCIE1
 343         pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
 344         hose = &pcie1_hose;
 345         pcie_ep = (host_agent <= 1) || (host_agent == 4) || (host_agent == 5);
 346         pcie_configured  = (io_sel & 6) || (io_sel == 0xE) || (io_sel == 0xF);
 347         r = hose->regions;
 348
 349         if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)) {
 350                 printf("\n    PCIE1 connected to Slot 2 as %s (base addr %x)",
 351                                 pcie_ep ? "End Point" : "Root Complex",
 352                                 (uint)pci);
 353                 if (pci->pme_msg_det) {
 354                         pci->pme_msg_det = 0xffffffff;
 355                         debug(" with errors.  Clearing.  Now 0x%08x",
 356                                 pci->pme_msg_det);
 357                 }
 358                 printf("\n");
 359
 360                 /* inbound */
 361                 r += fsl_pci_setup_inbound_windows(r);
 362
 363                 /* outbound memory */
 364                 pci_set_region(r++,
 365                                 CONFIG_SYS_PCIE1_MEM_BUS,
 366                                 CONFIG_SYS_PCIE1_MEM_PHYS,
 367                                 CONFIG_SYS_PCIE1_MEM_SIZE,
 368                                 PCI_REGION_MEM);
 369
 370                 /* outbound io */
 371                 pci_set_region(r++,
 372                                 CONFIG_SYS_PCIE1_IO_BUS,
 373                                 CONFIG_SYS_PCIE1_IO_PHYS,
 374                                 CONFIG_SYS_PCIE1_IO_SIZE,
 375                                 PCI_REGION_IO);
 376
 377                 hose->region_count = r - hose->regions;
 378                 hose->first_busno = first_free_busno;
 379
 380                 fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
 381
 382                 first_free_busno = hose->last_busno+1;
 383                 printf("    PCIE1 on bus %02x - %02x\n",
 384                         hose->first_busno, hose->last_busno);
 385
 386         } else {
 387                 printf("    PCIE1: disabled\n");
 388         }
 389 #else
 390         gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
 391 #endif
 392 }
 393 #endif
 394
 395 int board_early_init_r(void)
 396 {
 397         const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
 398         const u8 flash_esel = 2;
 399
 400         /*
 401          * Remap Boot flash + PROMJET region to caching-inhibited
 402          * so that flash can be erased properly.
 403          */
 404
 405         /* Flush d-cache and invalidate i-cache of any FLASH data */
 406         flush_dcache();
 407         invalidate_icache();
 408
 409         /* invalidate existing TLB entry for flash + promjet */
 410         disable_tlb(flash_esel);
 411
 412         set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
 413                         MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 414                         0, flash_esel, BOOKE_PAGESZ_256M, 1);
 415
 416         return 0;
 417 }
 418
 419 #ifdef CONFIG_GET_CLK_FROM_ICS307
 420 /* decode S[0-2] to Output Divider (OD) */
 421 static unsigned char ics307_S_to_OD[] = {
 422         10, 2, 8, 4, 5, 7, 3, 6
 423 };
 424
 425 /* Calculate frequency being generated by ICS307-02 clock chip based upon
 426  * the control bytes being programmed into it. */
 427 /* XXX: This function should probably go into a common library */
 428 static unsigned long
 429 ics307_clk_freq(unsigned char cw0, unsigned char cw1, unsigned char cw2)
 430 {
 431         const unsigned long InputFrequency = CONFIG_ICS307_REFCLK_HZ;
 432         unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1);
 433         unsigned long RDW = cw2 & 0x7F;
 434         unsigned long OD = ics307_S_to_OD[cw0 & 0x7];
 435         unsigned long freq;
 436
 437         /* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */
 438
 439         /* cw0:  C1 C0 TTL F1 F0 S2 S1 S0
 440          * cw1:  V8 V7 V6 V5 V4 V3 V2 V1
 441          * cw2:  V0 R6 R5 R4 R3 R2 R1 R0
 442          *
 443          * R6:R0 = Reference Divider Word (RDW)
 444          * V8:V0 = VCO Divider Word (VDW)
 445          * S2:S0 = Output Divider Select (OD)
 446          * F1:F0 = Function of CLK2 Output
 447          * TTL = duty cycle
 448          * C1:C0 = internal load capacitance for cyrstal
 449          */
 450
 451         /* Adding 1 to get a "nicely" rounded number, but this needs
 452          * more tweaking to get a "properly" rounded number. */
 453
 454         freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD));
 455
 456         debug("ICS307: CW[0-2]: %02X %02X %02X => %lu Hz\n", cw0, cw1, cw2,
 457                         freq);
 458         return freq;
 459 }
 460
 461 unsigned long get_board_sys_clk(ulong dummy)
 462 {
 463         return gd->bus_clk;
 464 }
 465
 466 unsigned long get_board_ddr_clk(ulong dummy)
 467 {
 468         return gd->mem_clk;
 469 }
 470
 471 unsigned long
 472 calculate_board_sys_clk(ulong dummy)
 473 {
 474         ulong val;
 475         u8 *pixis_base = (u8 *)PIXIS_BASE;
 476
 477         val = ics307_clk_freq(
 478             in_8(pixis_base + PIXIS_VSYSCLK0),
 479             in_8(pixis_base + PIXIS_VSYSCLK1),
 480             in_8(pixis_base + PIXIS_VSYSCLK2));
 481         debug("sysclk val = %lu\n", val);
 482         return val;
 483 }
 484
 485 unsigned long
 486 calculate_board_ddr_clk(ulong dummy)
 487 {
 488         ulong val;
 489         u8 *pixis_base = (u8 *)PIXIS_BASE;
 490
 491         val = ics307_clk_freq(
 492             in_8(pixis_base + PIXIS_VDDRCLK0),
 493             in_8(pixis_base + PIXIS_VDDRCLK1),
 494             in_8(pixis_base + PIXIS_VDDRCLK2));
 495         debug("ddrclk val = %lu\n", val);
 496         return val;
 497 }
 498 #else
 499 unsigned long get_board_sys_clk(ulong dummy)
 500 {
 501         u8 i;
 502         ulong val = 0;
 503         u8 *pixis_base = (u8 *)PIXIS_BASE;
 504
 505         i = in_8(pixis_base + PIXIS_SPD);
 506         i &= 0x07;
 507
 508         switch (i) {
 509                 case 0:
 510                         val = 33333333;
 511                         break;
 512                 case 1:
 513                         val = 40000000;
 514                         break;
 515                 case 2:
 516                         val = 50000000;
 517                         break;
 518                 case 3:
 519                         val = 66666666;
 520                         break;
 521                 case 4:
 522                         val = 83333333;
 523                         break;
 524                 case 5:
 525                         val = 100000000;
 526                         break;
 527                 case 6:
 528                         val = 133333333;
 529                         break;
 530                 case 7:
 531                         val = 166666666;
 532                         break;
 533         }
 534
 535         return val;
 536 }
 537
 538 unsigned long get_board_ddr_clk(ulong dummy)
 539 {
 540         u8 i;
 541         ulong val = 0;
 542         u8 *pixis_base = (u8 *)PIXIS_BASE;
 543
 544         i = in_8(pixis_base + PIXIS_SPD);
 545         i &= 0x38;
 546         i >>= 3;
 547
 548         switch (i) {
 549                 case 0:
 550                         val = 33333333;
 551                         break;
 552                 case 1:
 553                         val = 40000000;
 554                         break;
 555                 case 2:
 556                         val = 50000000;
 557                         break;
 558                 case 3:
 559                         val = 66666666;
 560                         break;
 561                 case 4:
 562                         val = 83333333;
 563                         break;
 564                 case 5:
 565                         val = 100000000;
 566                         break;
 567                 case 6:
 568                         val = 133333333;
 569                         break;
 570                 case 7:
 571                         val = 166666666;
 572                         break;
 573         }
 574         return val;
 575 }
 576 #endif
 577
 578 #ifdef CONFIG_TSEC_ENET
 579 int board_eth_init(bd_t *bis)
 580 {
 581         struct tsec_info_struct tsec_info[4];
 582         volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 583         int num = 0;
 584
 585 #ifdef CONFIG_TSEC1
 586         SET_STD_TSEC_INFO(tsec_info[num], 1);
 587         num++;
 588 #endif
 589 #ifdef CONFIG_TSEC2
 590         SET_STD_TSEC_INFO(tsec_info[num], 2);
 591         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
 592                 tsec_info[num].flags |= TSEC_SGMII;
 593         num++;
 594 #endif
 595 #ifdef CONFIG_TSEC3
 596         SET_STD_TSEC_INFO(tsec_info[num], 3);
 597         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
 598                 tsec_info[num].flags |= TSEC_SGMII;
 599         num++;
 600 #endif
 601
 602         if (!num) {
 603                 printf("No TSECs initialized\n");
 604
 605                 return 0;
 606         }
 607
 608 #ifdef CONFIG_FSL_SGMII_RISER
 609         fsl_sgmii_riser_init(tsec_info, num);
 610 #endif
 611
 612         tsec_eth_init(bis, tsec_info, num);
 613
 614         return pci_eth_init(bis);
 615 }
 616 #endif
 617
 618 #if defined(CONFIG_OF_BOARD_SETUP)
 619 void ft_board_setup(void *blob, bd_t *bd)
 620 {
 621         phys_addr_t base;
 622         phys_size_t size;
 623
 624         ft_cpu_setup(blob, bd);
 625
 626         base = getenv_bootm_low();
 627         size = getenv_bootm_size();
 628
 629         fdt_fixup_memory(blob, (u64)base, (u64)size);
 630
 631 #ifdef CONFIG_PCIE3
 632         ft_fsl_pci_setup(blob, "pci0", &pcie3_hose);
 633 #endif
 634 #ifdef CONFIG_PCIE2
 635         ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
 636 #endif
 637 #ifdef CONFIG_PCIE1
 638         ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
 639 #endif
 640 #ifdef CONFIG_FSL_SGMII_RISER
 641         fsl_sgmii_riser_fdt_fixup(blob);
 642 #endif
 643 }
 644 #endif
 645
 646 #ifdef CONFIG_MP
 647 void board_lmb_reserve(struct lmb *lmb)
 648 {
 649         cpu_mp_lmb_reserve(lmb);
 650 }
 651 #endif