2 * Copyright 2007-2012 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/processor.h>
12 #include <asm/cache.h>
13 #include <asm/immap_85xx.h>
14 #include <asm/fsl_pci.h>
15 #include <asm/fsl_ddr_sdram.h>
17 #include <asm/fsl_serdes.h>
20 #include <fdt_support.h>
23 #include <asm/fsl_law.h>
26 #include "../common/ngpixis.h"
27 #include "../common/sgmii_riser.h"
29 DECLARE_GLOBAL_DATA_PTR;
31 int board_early_init_f(void)
34 ccsr_gur_t *gur = (ccsr_gur_t *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
36 setbits_be32(&gur->pmuxcr,
37 (MPC85xx_PMUXCR_SDHC_CD |
38 MPC85xx_PMUXCR_SDHC_WP));
48 printf("Board: P2020DS Sys ID: 0x%02x, "
49 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
50 in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
52 sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
53 sw = (sw & PIXIS_LBMAP_MASK) >> PIXIS_LBMAP_SHIFT;
56 /* The lower two bits are the actual vbank number */
57 printf("vBank: %d\n", sw & 3);
64 #if !defined(CONFIG_DDR_SPD)
66 * Fixed sdram init -- doesn't use serial presence detect.
69 phys_size_t fixed_sdram(void)
71 volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
74 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
75 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
76 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
77 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
78 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
79 ddr->sdram_md_cntl = CONFIG_SYS_DDR_MODE_CTRL;
80 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
81 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
82 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
83 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
84 ddr->ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL;
85 ddr->ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL;
86 ddr->ddr_cdr1 = CONFIG_SYS_DDR_CDR1;
87 ddr->timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4;
88 ddr->timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5;
90 if (!strcmp("performance", getenv("perf_mode"))) {
91 /* Performance Mode Values */
93 ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG_PERF;
94 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS_PERF;
95 ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS_PERF;
96 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_PERF;
97 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_PERF;
103 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL_PERF;
105 /* Stable Mode Values */
107 ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG;
108 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
109 ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS;
110 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
111 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
113 /* ECC will be assumed in stable mode */
114 ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
115 ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
116 ddr->err_sbe = CONFIG_SYS_DDR_SBE;
122 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
125 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
127 debug("DDR - 1st controller: memory initializing\n");
129 * Poll until memory is initialized.
130 * 512 Meg at 400 might hit this 200 times or so.
132 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0)
134 debug("DDR: memory initialized\n\n");
139 if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
140 CONFIG_SYS_SDRAM_SIZE * 1024 * 1024,
141 LAW_TRGT_IF_DDR) < 0) {
142 printf("ERROR setting Local Access Windows for DDR\n");
146 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
152 void pci_init_board(void)
154 fsl_pcie_init_board(0);
158 int board_early_init_r(void)
160 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
161 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
164 * Remap Boot flash + PROMJET region to caching-inhibited
165 * so that flash can be erased properly.
168 /* Flush d-cache and invalidate i-cache of any FLASH data */
172 /* invalidate existing TLB entry for flash + promjet */
173 disable_tlb(flash_esel);
175 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
176 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
177 0, flash_esel, BOOKE_PAGESZ_256M, 1);
182 #ifdef CONFIG_TSEC_ENET
183 int board_eth_init(bd_t *bis)
185 struct fsl_pq_mdio_info mdio_info;
186 struct tsec_info_struct tsec_info[4];
190 SET_STD_TSEC_INFO(tsec_info[num], 1);
194 SET_STD_TSEC_INFO(tsec_info[num], 2);
195 if (is_serdes_configured(SGMII_TSEC2)) {
196 puts("eTSEC2 is in sgmii mode.\n");
197 tsec_info[num].flags |= TSEC_SGMII;
202 SET_STD_TSEC_INFO(tsec_info[num], 3);
203 if (is_serdes_configured(SGMII_TSEC3)) {
204 puts("eTSEC3 is in sgmii mode.\n");
205 tsec_info[num].flags |= TSEC_SGMII;
211 printf("No TSECs initialized\n");
216 #ifdef CONFIG_FSL_SGMII_RISER
217 fsl_sgmii_riser_init(tsec_info, num);
220 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
221 mdio_info.name = DEFAULT_MII_NAME;
223 fsl_pq_mdio_init(bis, &mdio_info);
225 tsec_eth_init(bis, tsec_info, num);
227 return pci_eth_init(bis);
231 #if defined(CONFIG_OF_BOARD_SETUP)
232 void ft_board_setup(void *blob, bd_t *bd)
237 ft_cpu_setup(blob, bd);
239 base = getenv_bootm_low();
240 size = getenv_bootm_size();
242 fdt_fixup_memory(blob, (u64)base, (u64)size);
244 #ifdef CONFIG_HAS_FSL_DR_USB
245 fdt_fixup_dr_usb(blob, bd);
250 #ifdef CONFIG_FSL_SGMII_RISER
251 fsl_sgmii_riser_fdt_fixup(blob);