2 * Copyright 2007-2011 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
28 #include <asm/cache.h>
29 #include <asm/immap_85xx.h>
30 #include <asm/fsl_pci.h>
31 #include <asm/fsl_ddr_sdram.h>
33 #include <asm/fsl_serdes.h>
36 #include <fdt_support.h>
39 #include <asm/fsl_law.h>
42 #include "../common/ngpixis.h"
43 #include "../common/sgmii_riser.h"
45 DECLARE_GLOBAL_DATA_PTR;
47 int board_early_init_f(void)
50 ccsr_gur_t *gur = (ccsr_gur_t *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
52 setbits_be32(&gur->pmuxcr,
53 (MPC85xx_PMUXCR_SDHC_CD |
54 MPC85xx_PMUXCR_SDHC_WP));
64 printf("Board: P2020DS Sys ID: 0x%02x, "
65 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
66 in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
68 sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
69 sw = (sw & PIXIS_LBMAP_MASK) >> PIXIS_LBMAP_SHIFT;
72 /* The lower two bits are the actual vbank number */
73 printf("vBank: %d\n", sw & 3);
80 #if !defined(CONFIG_DDR_SPD)
82 * Fixed sdram init -- doesn't use serial presence detect.
85 phys_size_t fixed_sdram(void)
87 volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
90 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
91 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
92 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
93 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
94 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
95 ddr->sdram_md_cntl = CONFIG_SYS_DDR_MODE_CTRL;
96 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
97 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
98 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
99 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
100 ddr->ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL;
101 ddr->ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL;
102 ddr->ddr_cdr1 = CONFIG_SYS_DDR_CDR1;
103 ddr->timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4;
104 ddr->timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5;
106 if (!strcmp("performance", getenv("perf_mode"))) {
107 /* Performance Mode Values */
109 ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG_PERF;
110 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS_PERF;
111 ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS_PERF;
112 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_PERF;
113 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_PERF;
119 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL_PERF;
121 /* Stable Mode Values */
123 ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG;
124 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
125 ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS;
126 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
127 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
129 /* ECC will be assumed in stable mode */
130 ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
131 ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
132 ddr->err_sbe = CONFIG_SYS_DDR_SBE;
138 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
141 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
143 debug("DDR - 1st controller: memory initializing\n");
145 * Poll until memory is initialized.
146 * 512 Meg at 400 might hit this 200 times or so.
148 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0)
150 debug("DDR: memory initialized\n\n");
155 if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
156 CONFIG_SYS_SDRAM_SIZE * 1024 * 1024,
157 LAW_TRGT_IF_DDR) < 0) {
158 printf("ERROR setting Local Access Windows for DDR\n");
162 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
168 void pci_init_board(void)
170 fsl_pcie_init_board(0);
174 int board_early_init_r(void)
176 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
177 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
180 * Remap Boot flash + PROMJET region to caching-inhibited
181 * so that flash can be erased properly.
184 /* Flush d-cache and invalidate i-cache of any FLASH data */
188 /* invalidate existing TLB entry for flash + promjet */
189 disable_tlb(flash_esel);
191 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
192 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
193 0, flash_esel, BOOKE_PAGESZ_256M, 1);
198 #ifdef CONFIG_TSEC_ENET
199 int board_eth_init(bd_t *bis)
201 struct fsl_pq_mdio_info mdio_info;
202 struct tsec_info_struct tsec_info[4];
206 SET_STD_TSEC_INFO(tsec_info[num], 1);
210 SET_STD_TSEC_INFO(tsec_info[num], 2);
211 if (is_serdes_configured(SGMII_TSEC2)) {
212 puts("eTSEC2 is in sgmii mode.\n");
213 tsec_info[num].flags |= TSEC_SGMII;
218 SET_STD_TSEC_INFO(tsec_info[num], 3);
219 if (is_serdes_configured(SGMII_TSEC3)) {
220 puts("eTSEC3 is in sgmii mode.\n");
221 tsec_info[num].flags |= TSEC_SGMII;
227 printf("No TSECs initialized\n");
232 #ifdef CONFIG_FSL_SGMII_RISER
233 fsl_sgmii_riser_init(tsec_info, num);
236 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
237 mdio_info.name = DEFAULT_MII_NAME;
239 fsl_pq_mdio_init(bis, &mdio_info);
241 tsec_eth_init(bis, tsec_info, num);
243 return pci_eth_init(bis);
247 #if defined(CONFIG_OF_BOARD_SETUP)
248 void ft_board_setup(void *blob, bd_t *bd)
253 ft_cpu_setup(blob, bd);
255 base = getenv_bootm_low();
256 size = getenv_bootm_size();
258 fdt_fixup_memory(blob, (u64)base, (u64)size);
262 #ifdef CONFIG_FSL_SGMII_RISER
263 fsl_sgmii_riser_fdt_fixup(blob);