1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2013 Freescale Semiconductor, Inc.
15 #include <asm/processor.h>
17 #include <asm/cache.h>
18 #include <asm/immap_85xx.h>
19 #include <asm/fsl_pci.h>
20 #include <fsl_ddr_sdram.h>
22 #include <asm/fsl_law.h>
23 #include <asm/fsl_lbc.h>
26 #include <linux/libfdt.h>
27 #include <fdt_support.h>
31 #include <asm/fsl_serdes.h>
34 #define SYSCLK_64 64000000
35 #define SYSCLK_66 66666666
37 unsigned long get_board_sys_clk(ulong dummy)
39 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
40 par_io_t *par_io = (par_io_t *) &(gur->qe_par_io);
41 unsigned int cpdat_val = 0;
43 /* Set-up up pin muxing based on board switch settings */
44 cpdat_val = par_io[1].cpdat;
46 /* Check switch setting for SYSCLK select (PB3) */
47 if (cpdat_val & 0x10000000)
57 #define PCA_IOPORT_I2C_ADDR 0x23
58 #define PCA_IOPORT_OUTPUT_CMD 0x2
59 #define PCA_IOPORT_CFG_CMD 0x6
61 const qe_iop_conf_t qe_iop_conf_tab[] = {
63 #ifdef CONFIG_TWR_P1025
68 /* GPIO for switch options */
69 {1, 2, 2, 0, 0}, /* PROFIBUS_MODE_SEL */
70 {1, 3, 2, 0, 0}, /* SYS_CLK_SELECT */
71 {1, 29, 2, 0, 0}, /* LOCALBUS_QE_MUXSEL */
72 {1, 30, 2, 0, 0}, /* ETH_TDM_SEL */
75 {1, 19, 1, 0, 1}, /* QE_MUX_MDC */
78 {1, 20, 3, 0, 1}, /* QE_MUX_MDIO */
81 {0, 23, 2, 0, 2}, /* CLK12 */
82 {0, 24, 2, 0, 1}, /* CLK9 */
83 {0, 7, 1, 0, 2}, /* ENET1_TXD0_SER1_TXD0 */
84 {0, 9, 1, 0, 2}, /* ENET1_TXD1_SER1_TXD1 */
85 {0, 11, 1, 0, 2}, /* ENET1_TXD2_SER1_TXD2 */
86 {0, 12, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */
87 {0, 6, 2, 0, 2}, /* ENET1_RXD0_SER1_RXD0 */
88 {0, 10, 2, 0, 2}, /* ENET1_RXD1_SER1_RXD1 */
89 {0, 14, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2 */
90 {0, 15, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3 */
91 {0, 5, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */
92 {0, 13, 1, 0, 2}, /* ENET1_TX_ER */
93 {0, 4, 2, 0, 2}, /* ENET1_RX_DV_SER1_CTS_B */
94 {0, 8, 2, 0, 2}, /* ENET1_RX_ER_SER1_CD_B */
95 {0, 17, 2, 0, 2}, /* ENET1_CRS */
96 {0, 16, 2, 0, 2}, /* ENET1_COL */
99 {1, 11, 2, 0, 1}, /* CLK13 */
100 {1, 7, 1, 0, 2}, /* ENET5_TXD0_SER5_TXD0 */
101 {1, 10, 1, 0, 2}, /* ENET5_TXD1_SER5_TXD1 */
102 {1, 6, 2, 0, 2}, /* ENET5_RXD0_SER5_RXD0 */
103 {1, 9, 2, 0, 2}, /* ENET5_RXD1_SER5_RXD1 */
104 {1, 5, 1, 0, 2}, /* ENET5_TX_EN_SER5_RTS_B */
105 {1, 4, 2, 0, 2}, /* ENET5_RX_DV_SER5_CTS_B */
106 {1, 8, 2, 0, 2}, /* ENET5_RX_ER_SER5_CD_B */
108 /* TDMA - clock option is configured in OS based on board setting */
109 {1, 23, 2, 0, 2}, /* TDMA_TXD */
110 {1, 25, 2, 0, 2}, /* TDMA_RXD */
111 {1, 26, 1, 0, 2}, /* TDMA_SYNC */
114 {0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */
118 int board_early_init_f(void)
120 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
122 setbits_be32(&gur->pmuxcr,
123 (MPC85xx_PMUXCR_SDHC_CD | MPC85xx_PMUXCR_SDHC_WP));
125 /* SDHC_DAT[4:7] not exposed to pins (use as SPI) */
126 clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
133 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
136 printf("Board: %s\n", CONFIG_BOARDNAME);
138 boot_status = ((gur->porbmsr) >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf;
140 if (boot_status == PORBMSR_ROMLOC_NOR)
142 else if (boot_status == PORBMSR_ROMLOC_SDHC)
152 void pci_init_board(void)
154 fsl_pcie_init_board(0);
158 int board_early_init_r(void)
160 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
161 int flash_esel = find_tlb_idx((void *)flashbase, 1);
164 * Remap Boot flash region to caching-inhibited
165 * so that flash can be erased properly.
168 /* Flush d-cache and invalidate i-cache of any FLASH data */
172 if (flash_esel == -1) {
173 /* very unlikely unless something is messed up */
174 puts("Error: Could not find TLB for FLASH BASE\n");
175 flash_esel = 2; /* give our best effort to continue */
177 /* invalidate existing TLB entry for flash */
178 disable_tlb(flash_esel);
181 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
182 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
183 0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */
187 int board_eth_init(bd_t *bis)
189 struct fsl_pq_mdio_info mdio_info;
190 struct tsec_info_struct tsec_info[4];
191 ccsr_gur_t *gur __attribute__((unused)) =
192 (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
196 SET_STD_TSEC_INFO(tsec_info[num], 1);
200 SET_STD_TSEC_INFO(tsec_info[num], 2);
201 if (is_serdes_configured(SGMII_TSEC2)) {
202 printf("eTSEC2 is in sgmii mode.\n");
203 tsec_info[num].flags |= TSEC_SGMII;
208 SET_STD_TSEC_INFO(tsec_info[num], 3);
213 printf("No TSECs initialized\n");
217 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
218 mdio_info.name = DEFAULT_MII_NAME;
220 fsl_pq_mdio_init(bis, &mdio_info);
222 tsec_eth_init(bis, tsec_info, num);
224 #if defined(CONFIG_UEC_ETH)
225 /* QE0 and QE3 need to be exposed for UCC1
226 * and UCC5 Eth mode (in PMUXCR register).
227 * Currently QE/LBC muxed pins assumed to be
228 * LBC for U-Boot and PMUXCR updated by OS if required */
230 uec_standard_init(bis);
233 return pci_eth_init(bis);
236 #if defined(CONFIG_QE)
237 static void fdt_board_fixup_qe_pins(void *blob)
241 if (!hwconfig("qe")) {
242 /* For QE and eLBC pins multiplexing,
243 * When don't use QE function, remove
244 * qe node from dt blob.
246 node = fdt_path_offset(blob, "/qe");
248 fdt_del_node(blob, node);
250 /* For TWR Peripheral Modules - TWR-SER2
251 * board only can support Signal Port MII,
252 * so delete one UEC node when use MII port.
255 node = fdt_path_offset(blob, "/qe/ucc@2400");
257 node = fdt_path_offset(blob, "/qe/ucc@2000");
259 fdt_del_node(blob, node);
266 #ifdef CONFIG_OF_BOARD_SETUP
267 int ft_board_setup(void *blob, bd_t *bd)
272 ft_cpu_setup(blob, bd);
274 base = env_get_bootm_low();
275 size = env_get_bootm_size();
277 fdt_fixup_memory(blob, (u64)base, (u64)size);
282 do_fixup_by_compat(blob, "fsl,qe", "status", "okay",
285 #if defined(CONFIG_TWR_P1025)
286 fdt_board_fixup_qe_pins(blob);
288 fsl_fdt_fixup_dr_usb(blob, bd);