1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2010-2011, 2013 Freescale Semiconductor, Inc.
13 #include <asm/processor.h>
15 #include <asm/cache.h>
16 #include <asm/immap_85xx.h>
17 #include <asm/fsl_pci.h>
18 #include <fsl_ddr_sdram.h>
20 #include <asm/fsl_law.h>
21 #include <asm/fsl_lbc.h>
24 #include <linux/libfdt.h>
25 #include <fdt_support.h>
30 #include <asm/fsl_serdes.h>
35 #define GPIO_GETH_SW_PORT 1
36 #define GPIO_GETH_SW_PIN 29
37 #define GPIO_GETH_SW_DATA (1 << (31 - GPIO_GETH_SW_PIN))
39 #define GPIO_SLIC_PORT 1
40 #define GPIO_SLIC_PIN 30
41 #define GPIO_SLIC_DATA (1 << (31 - GPIO_SLIC_PIN))
43 #if defined(CONFIG_TARGET_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
44 #define GPIO_DDR_RST_PORT 1
45 #define GPIO_DDR_RST_PIN 8
46 #define GPIO_DDR_RST_DATA (1 << (31 - GPIO_DDR_RST_PIN))
48 #define GPIO_2BIT_MASK (0x3 << (32 - (GPIO_DDR_RST_PIN + 1) * 2))
51 #if defined(CONFIG_TARGET_P1025RDB) || defined(CONFIG_TARGET_P1021RDB)
52 #define PCA_IOPORT_I2C_ADDR 0x23
53 #define PCA_IOPORT_OUTPUT_CMD 0x2
54 #define PCA_IOPORT_CFG_CMD 0x6
55 #define PCA_IOPORT_QE_PIN_ENABLE 0xf8
56 #define PCA_IOPORT_QE_TDM_ENABLE 0xf6
59 const qe_iop_conf_t qe_iop_conf_tab[] = {
61 {1, 1, 2, 0, 0}, /* GPIO7/PB1 - LOAD_DEFAULT_N */
62 #if defined(CONFIG_TARGET_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
63 {1, 8, 1, 1, 0}, /* GPIO10/PB8 - DDR_RST */
65 {0, 15, 1, 0, 0}, /* GPIO11/A15 - WDI */
66 {GPIO_GETH_SW_PORT, GPIO_GETH_SW_PIN, 1, 0, 0}, /* RST_GETH_SW_N */
67 {GPIO_SLIC_PORT, GPIO_SLIC_PIN, 1, 0, 0}, /* RST_SLIC_N */
69 #ifdef CONFIG_TARGET_P1025RDB
71 {1, 19, 1, 0, 1}, /* QE_MUX_MDC */
74 {1, 20, 3, 0, 1}, /* QE_MUX_MDIO */
77 {0, 23, 2, 0, 2}, /* CLK12 */
78 {0, 24, 2, 0, 1}, /* CLK9 */
79 {0, 7, 1, 0, 2}, /* ENET1_TXD0_SER1_TXD0 */
80 {0, 9, 1, 0, 2}, /* ENET1_TXD1_SER1_TXD1 */
81 {0, 11, 1, 0, 2}, /* ENET1_TXD2_SER1_TXD2 */
82 {0, 12, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */
83 {0, 6, 2, 0, 2}, /* ENET1_RXD0_SER1_RXD0 */
84 {0, 10, 2, 0, 2}, /* ENET1_RXD1_SER1_RXD1 */
85 {0, 14, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2 */
86 {0, 15, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3 */
87 {0, 5, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */
88 {0, 13, 1, 0, 2}, /* ENET1_TX_ER */
89 {0, 4, 2, 0, 2}, /* ENET1_RX_DV_SER1_CTS_B */
90 {0, 8, 2, 0, 2}, /* ENET1_RX_ER_SER1_CD_B */
91 {0, 17, 2, 0, 2}, /* ENET1_CRS */
92 {0, 16, 2, 0, 2}, /* ENET1_COL */
95 {1, 11, 2, 0, 1}, /* CLK13 */
96 {1, 7, 1, 0, 2}, /* ENET5_TXD0_SER5_TXD0 */
97 {1, 10, 1, 0, 2}, /* ENET5_TXD1_SER5_TXD1 */
98 {1, 6, 2, 0, 2}, /* ENET5_RXD0_SER5_RXD0 */
99 {1, 9, 2, 0, 2}, /* ENET5_RXD1_SER5_RXD1 */
100 {1, 5, 1, 0, 2}, /* ENET5_TX_EN_SER5_RTS_B */
101 {1, 4, 2, 0, 2}, /* ENET5_RX_DV_SER5_CTS_B */
102 {1, 8, 2, 0, 2}, /* ENET5_RX_ER_SER5_CD_B */
105 {0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */
118 u8 status_led; /* offset: 0x8 */
119 u8 fxo_led; /* offset: 0x9 */
120 u8 fxs_led; /* offset: 0xa */
122 u8 system_rst; /* offset: 0xd */
128 #define CPLD_WD_CFG 0x03
129 #define CPLD_RST_BSW 0x00
130 #define CPLD_RST_BWD 0x00
131 #define CPLD_BYPASS_EN 0x03
132 #define CPLD_STATUS_LED 0x01
133 #define CPLD_FXO_LED 0x01
134 #define CPLD_FXS_LED 0x0F
135 #define CPLD_SYS_RST 0x00
137 void board_cpld_init(void)
139 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
141 out_8(&cpld_data->wd_cfg, CPLD_WD_CFG);
142 out_8(&cpld_data->status_led, CPLD_STATUS_LED);
143 out_8(&cpld_data->fxo_led, CPLD_FXO_LED);
144 out_8(&cpld_data->fxs_led, CPLD_FXS_LED);
145 out_8(&cpld_data->system_rst, CPLD_SYS_RST);
148 void board_gpio_init(void)
151 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
152 par_io_t *par_io = (par_io_t *) &(gur->qe_par_io);
154 #if defined(CONFIG_TARGET_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
156 setbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA);
158 clrbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA);
160 setbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA);
162 clrbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdir1, GPIO_2BIT_MASK);
164 /* Enable VSC7385 switch */
165 setbits_be32(&par_io[GPIO_GETH_SW_PORT].cpdat, GPIO_GETH_SW_DATA);
168 setbits_be32(&par_io[GPIO_SLIC_PORT].cpdat, GPIO_SLIC_DATA);
171 ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
174 * GPIO10 DDR Reset, open drain
175 * GPIO7 LOAD_DEFAULT_N Input
176 * GPIO11 WDI (watchdog input)
177 * GPIO12 Ethernet Switch Reset
181 setbits_be32(&pgpio->gpdir, 0x02130000);
182 #if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SPL)
183 /* init DDR3 reset signal */
184 setbits_be32(&pgpio->gpdir, 0x00200000);
185 setbits_be32(&pgpio->gpodr, 0x00200000);
186 clrbits_be32(&pgpio->gpdat, 0x00200000);
188 setbits_be32(&pgpio->gpdat, 0x00200000);
190 clrbits_be32(&pgpio->gpdir, 0x00200000);
193 #ifdef CONFIG_VSC7385_ENET
194 /* reset VSC7385 Switch */
195 setbits_be32(&pgpio->gpdir, 0x00080000);
196 setbits_be32(&pgpio->gpdat, 0x00080000);
201 setbits_be32(&pgpio->gpdir, 0x00040000);
202 setbits_be32(&pgpio->gpdat, 0x00040000);
207 int board_early_init_f(void)
209 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
211 setbits_be32(&gur->pmuxcr,
212 (MPC85xx_PMUXCR_SDHC_CD | MPC85xx_PMUXCR_SDHC_WP));
213 clrbits_be32(&gur->sdhcdcr, SDHCDCR_CD_INV);
215 clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
216 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TDM_ENA);
226 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
227 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
228 u8 in, out, io_config, val;
230 printf("Board: %s CPLD: V%d.%d PCBA: V%d.0\n", CONFIG_BOARDNAME,
231 in_8(&cpld_data->cpld_rev_major) & 0x0F,
232 in_8(&cpld_data->cpld_rev_minor) & 0x0F,
233 in_8(&cpld_data->pcba_rev) & 0x0F);
235 /* Initialize i2c early for rom_loc and flash bank information */
236 i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM);
238 if (i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 0, 1, &in, 1) < 0 ||
239 i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 1, 1, &out, 1) < 0 ||
240 i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 3, 1, &io_config, 1) < 0) {
241 printf("Error reading i2c boot information!\n");
242 return 0; /* Don't want to hang() on this error */
245 val = (in & io_config) | (out & (~io_config));
248 if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SD) {
251 } else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SPI) {
254 #ifdef __SW_BOOT_NAND
255 } else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_NAND) {
258 #ifdef __SW_BOOT_PCIE
259 } else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_PCIE) {
264 puts("nor lower bank");
266 puts("nor upper bank");
271 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
272 puts("SD/MMC : 8-bit Mode\n");
273 puts("eSPI : Disabled\n");
275 puts("SD/MMC : 4-bit Mode\n");
276 puts("eSPI : Enabled\n");
282 #if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI)
283 void pci_init_board(void)
285 fsl_pcie_init_board(0);
289 int board_early_init_r(void)
291 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
292 int flash_esel = find_tlb_idx((void *)flashbase, 1);
295 * Remap Boot flash region to caching-inhibited
296 * so that flash can be erased properly.
299 /* Flush d-cache and invalidate i-cache of any FLASH data */
303 if (flash_esel == -1) {
304 /* very unlikely unless something is messed up */
305 puts("Error: Could not find TLB for FLASH BASE\n");
306 flash_esel = 2; /* give our best effort to continue */
308 /* invalidate existing TLB entry for flash */
309 disable_tlb(flash_esel);
312 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
313 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,/* perms, wimge */
314 0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */
318 int board_eth_init(bd_t *bis)
320 struct fsl_pq_mdio_info mdio_info;
321 struct tsec_info_struct tsec_info[4];
322 ccsr_gur_t *gur __attribute__((unused)) =
323 (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
325 #ifdef CONFIG_VSC7385_ENET
327 unsigned int vscfw_addr;
331 SET_STD_TSEC_INFO(tsec_info[num], 1);
335 SET_STD_TSEC_INFO(tsec_info[num], 2);
336 if (is_serdes_configured(SGMII_TSEC2)) {
337 printf("eTSEC2 is in sgmii mode.\n");
338 tsec_info[num].flags |= TSEC_SGMII;
343 SET_STD_TSEC_INFO(tsec_info[num], 3);
348 printf("No TSECs initialized\n");
352 #ifdef CONFIG_VSC7385_ENET
353 /* If a VSC7385 microcode image is present, then upload it. */
354 tmp = env_get("vscfw_addr");
356 vscfw_addr = simple_strtoul(tmp, NULL, 16);
357 printf("uploading VSC7385 microcode from %x\n", vscfw_addr);
358 if (vsc7385_upload_firmware((void *) vscfw_addr,
359 CONFIG_VSC7385_IMAGE_SIZE))
360 puts("Failure uploading VSC7385 microcode.\n");
362 puts("No address specified for VSC7385 microcode.\n");
365 mdio_info.regs = TSEC_GET_MDIO_REGS_BASE(1);
366 mdio_info.name = DEFAULT_MII_NAME;
368 fsl_pq_mdio_init(bis, &mdio_info);
370 tsec_eth_init(bis, tsec_info, num);
372 #if defined(CONFIG_UEC_ETH)
373 /* QE0 and QE3 need to be exposed for UCC1 and UCC5 Eth mode */
374 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE0);
375 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE3);
377 uec_standard_init(bis);
380 return pci_eth_init(bis);
383 #if defined(CONFIG_QE) && \
384 (defined(CONFIG_TARGET_P1025RDB) || defined(CONFIG_TARGET_P1021RDB))
385 static void fdt_board_fixup_qe_pins(void *blob)
390 fsl_lbc_t *lbc = LBC_BASE_ADDR;
392 if (hwconfig("qe")) {
393 /* For QE and eLBC pins multiplexing,
394 * there is a PCA9555 device on P1025RDB.
395 * It control the multiplex pins' functions,
396 * and setting the PCA9555 can switch the
397 * function between QE and eLBC.
399 oldbus = i2c_get_bus_num();
402 val8 = PCA_IOPORT_QE_TDM_ENABLE;
404 val8 = PCA_IOPORT_QE_PIN_ENABLE;
405 i2c_write(PCA_IOPORT_I2C_ADDR, PCA_IOPORT_CFG_CMD,
407 i2c_write(PCA_IOPORT_I2C_ADDR, PCA_IOPORT_OUTPUT_CMD,
409 i2c_set_bus_num(oldbus);
410 /* if run QE TDM, Set ABSWP to implement
411 * conversion of addresses in the eLBC.
413 if (hwconfig("tdm")) {
414 set_lbc_or(2, CONFIG_PMC_OR_PRELIM);
415 set_lbc_br(2, CONFIG_PMC_BR_PRELIM);
416 setbits_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
419 node = fdt_path_offset(blob, "/qe");
421 fdt_del_node(blob, node);
428 #ifdef CONFIG_OF_BOARD_SETUP
429 int ft_board_setup(void *blob, bd_t *bd)
433 #if defined(CONFIG_TARGET_P1020RDB_PD) || defined(CONFIG_TARGET_P1020RDB_PC)
434 const char *soc_usb_compat = "fsl-usb2-dr";
435 int usb_err, usb1_off, usb2_off;
437 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
441 ft_cpu_setup(blob, bd);
443 base = env_get_bootm_low();
444 size = env_get_bootm_size();
446 fdt_fixup_memory(blob, (u64)base, (u64)size);
448 #if !defined(CONFIG_DM_PCI)
453 do_fixup_by_compat(blob, "fsl,qe", "status", "okay",
455 #if defined(CONFIG_TARGET_P1025RDB) || defined(CONFIG_TARGET_P1021RDB)
456 fdt_board_fixup_qe_pins(blob);
460 #if defined(CONFIG_HAS_FSL_DR_USB)
461 fsl_fdt_fixup_dr_usb(blob, bd);
464 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
465 /* Delete eLBC node as it is muxed with USB2 controller */
466 if (hwconfig("usb2")) {
467 const char *soc_elbc_compat = "fsl,p1020-elbc";
468 int off = fdt_node_offset_by_compatible(blob, -1,
471 printf("WARNING: could not find compatible node %s\n",
475 err = fdt_del_node(blob, off);
477 printf("WARNING: could not remove %s\n",
485 #if defined(CONFIG_TARGET_P1020RDB_PD) || defined(CONFIG_TARGET_P1020RDB_PC)
486 /* Delete USB2 node as it is muxed with eLBC */
487 usb1_off = fdt_node_offset_by_compatible(blob, -1,
490 printf("WARNING: could not find compatible node %s\n",
494 usb2_off = fdt_node_offset_by_compatible(blob, usb1_off,
497 printf("WARNING: could not find compatible node %s\n",
501 usb_err = fdt_del_node(blob, usb2_off);
503 printf("WARNING: could not remove %s\n", soc_usb_compat);