2 * Copyright 2009 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/immap_85xx.h>
26 #include <asm/fsl_ddr_sdram.h>
28 #include <asm/fsl_law.h>
30 extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
31 unsigned int ctrl_num);
33 #define DATARATE_400MHZ 400000000
34 #define DATARATE_533MHZ 533333333
35 #define DATARATE_667MHZ 666666666
36 #define DATARATE_800MHZ 800000000
38 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
39 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
40 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
41 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
42 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
43 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
44 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x00000000
45 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x00000000
46 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
47 #define CONFIG_SYS_DDR_RCW_1 0x00000000
48 #define CONFIG_SYS_DDR_RCW_2 0x00000000
49 #define CONFIG_SYS_DDR_CONTROL 0x43000000 /* Type = DDR2*/
50 #define CONFIG_SYS_DDR_CONTROL_2 0x24401000
51 #define CONFIG_SYS_DDR_TIMING_4 0x00000000
52 #define CONFIG_SYS_DDR_TIMING_5 0x00000000
54 #define CONFIG_SYS_DDR_TIMING_3_400 0x00010000
55 #define CONFIG_SYS_DDR_TIMING_0_400 0x00260802
56 #define CONFIG_SYS_DDR_TIMING_1_400 0x39355322
57 #define CONFIG_SYS_DDR_TIMING_2_400 0x1f9048ca
58 #define CONFIG_SYS_DDR_CLK_CTRL_400 0x02800000
59 #define CONFIG_SYS_DDR_MODE_1_400 0x00480432
60 #define CONFIG_SYS_DDR_MODE_2_400 0x00000000
61 #define CONFIG_SYS_DDR_INTERVAL_400 0x06180100
63 #define CONFIG_SYS_DDR_TIMING_3_533 0x00020000
64 #define CONFIG_SYS_DDR_TIMING_0_533 0x00260802
65 #define CONFIG_SYS_DDR_TIMING_1_533 0x4c47c432
66 #define CONFIG_SYS_DDR_TIMING_2_533 0x0f9848ce
67 #define CONFIG_SYS_DDR_CLK_CTRL_533 0x02800000
68 #define CONFIG_SYS_DDR_MODE_1_533 0x00040642
69 #define CONFIG_SYS_DDR_MODE_2_533 0x00000000
70 #define CONFIG_SYS_DDR_INTERVAL_533 0x08200100
72 #define CONFIG_SYS_DDR_TIMING_3_667 0x00030000
73 #define CONFIG_SYS_DDR_TIMING_0_667 0x55770802
74 #define CONFIG_SYS_DDR_TIMING_1_667 0x5f599543
75 #define CONFIG_SYS_DDR_TIMING_2_667 0x0fa074d1
76 #define CONFIG_SYS_DDR_CLK_CTRL_667 0x02800000
77 #define CONFIG_SYS_DDR_MODE_1_667 0x00040852
78 #define CONFIG_SYS_DDR_MODE_2_667 0x00000000
79 #define CONFIG_SYS_DDR_INTERVAL_667 0x0a280100
81 #define CONFIG_SYS_DDR_TIMING_3_800 0x00040000
82 #define CONFIG_SYS_DDR_TIMING_0_800 0x55770802
83 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b6543
84 #define CONFIG_SYS_DDR_TIMING_2_800 0x0fa074d1
85 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x02000000
86 #define CONFIG_SYS_DDR_MODE_1_800 0x00440862
87 #define CONFIG_SYS_DDR_MODE_2_800 0x00000000
88 #define CONFIG_SYS_DDR_INTERVAL_800 0x0a280100
90 fsl_ddr_cfg_regs_t ddr_cfg_regs_400 = {
91 .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
92 .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
93 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
94 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_400,
95 .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_400,
96 .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_400,
97 .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_400,
98 .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
99 .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
100 .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_400,
101 .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_400,
102 .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
103 .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_400,
104 .ddr_data_init = CONFIG_MEM_INIT_VALUE,
105 .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_400,
106 .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
107 .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
108 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
109 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
110 .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
111 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
112 .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
113 .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
114 .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
117 fsl_ddr_cfg_regs_t ddr_cfg_regs_533 = {
118 .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
119 .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
120 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
121 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_533,
122 .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_533,
123 .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_533,
124 .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_533,
125 .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
126 .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
127 .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_533,
128 .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_533,
129 .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
130 .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_533,
131 .ddr_data_init = CONFIG_MEM_INIT_VALUE,
132 .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_533,
133 .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
134 .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
135 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
136 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
137 .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
138 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
139 .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
140 .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
141 .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
144 fsl_ddr_cfg_regs_t ddr_cfg_regs_667 = {
145 .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
146 .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
147 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
148 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_667,
149 .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_667,
150 .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_667,
151 .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_667,
152 .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
153 .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
154 .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_667,
155 .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_667,
156 .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
157 .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_667,
158 .ddr_data_init = CONFIG_MEM_INIT_VALUE,
159 .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_667,
160 .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
161 .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
162 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
163 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
164 .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
165 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
166 .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
167 .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
168 .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
171 fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
172 .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
173 .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
174 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
175 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
176 .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
177 .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
178 .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
179 .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
180 .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
181 .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
182 .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
183 .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
184 .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
185 .ddr_data_init = CONFIG_MEM_INIT_VALUE,
186 .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
187 .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
188 .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
189 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
190 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
191 .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
192 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
193 .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
194 .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
195 .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
199 * Fixed sdram init -- doesn't use serial presence detect.
202 phys_size_t fixed_sdram (void)
207 get_sys_info(&sysinfo);
208 printf("Configuring DDR for %s MT/s data rate\n",
209 strmhz(buf, sysinfo.freqDDRBus));
211 if(sysinfo.freqDDRBus <= DATARATE_400MHZ)
212 fsl_ddr_set_memctl_regs(&ddr_cfg_regs_400, 0);
213 else if(sysinfo.freqDDRBus <= DATARATE_533MHZ)
214 fsl_ddr_set_memctl_regs(&ddr_cfg_regs_533, 0);
215 else if(sysinfo.freqDDRBus <= DATARATE_667MHZ)
216 fsl_ddr_set_memctl_regs(&ddr_cfg_regs_667, 0);
217 else if(sysinfo.freqDDRBus <= DATARATE_800MHZ)
218 fsl_ddr_set_memctl_regs(&ddr_cfg_regs_800, 0);
220 panic("Unsupported DDR data rate %s MT/s data rate\n",
221 strmhz(buf, sysinfo.freqDDRBus));
223 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
226 phys_size_t initdram(int board_type)
228 phys_size_t dram_size = 0;
230 dram_size = fixed_sdram();
231 set_ddr_laws(0, dram_size, LAW_TRGT_IF_DDR_1);
233 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
234 dram_size *= 0x100000;