board/freescale/p1023rdb/ddr.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2013 Freescale Semiconductor, Inc.
   4  */
   5
   6 #include <common.h>
   7 #include <asm/mmu.h>
   8 #include <asm/immap_85xx.h>
   9 #include <asm/processor.h>
  10 #include <fsl_ddr_sdram.h>
  11 #include <fsl_ddr_dimm_params.h>
  12 #include <asm/io.h>
  13 #include <asm/fsl_law.h>
  14
  15 /* CONFIG_SYS_DDR_RAW_TIMING */
  16 /*
  17  * Hynix H5TQ1G83TFR-H9C
  18  */
  19 dimm_params_t ddr_raw_timing = {
  20         .n_ranks = 1,
  21         .rank_density = 536870912u,
  22         .capacity = 536870912u,
  23         .primary_sdram_width = 32,
  24         .ec_sdram_width = 0,
  25         .registered_dimm = 0,
  26         .mirrored_dimm = 0,
  27         .n_row_addr = 14,
  28         .n_col_addr = 10,
  29         .n_banks_per_sdram_device = 8,
  30         .edc_config = 0,
  31         .burst_lengths_bitmask = 0x0c,
  32
  33         .tckmin_x_ps = 1875,
  34         .caslat_x = 0x1e << 4,  /* 5,6,7,8 */
  35         .taa_ps = 13125,
  36         .twr_ps = 18000,
  37         .trcd_ps = 13125,
  38         .trrd_ps = 7500,
  39         .trp_ps = 13125,
  40         .tras_ps = 37500,
  41         .trc_ps = 50625,
  42         .trfc_ps = 160000,
  43         .twtr_ps = 7500,
  44         .trtp_ps = 7500,
  45         .refresh_rate_ps = 7800000,
  46         .tfaw_ps = 37500,
  47 };
  48
  49 int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
  50                 unsigned int controller_number,
  51                 unsigned int dimm_number)
  52 {
  53         const char dimm_model[] = "Fixed DDR on board";
  54
  55         if ((controller_number == 0) && (dimm_number == 0)) {
  56                 memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
  57                 memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
  58                 memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
  59         }
  60
  61         return 0;
  62 }
  63
  64 void fsl_ddr_board_options(memctl_options_t *popts,
  65                                 dimm_params_t *pdimm,
  66                                 unsigned int ctrl_num)
  67 {
  68         int i;
  69         popts->clk_adjust = 6;
  70         popts->cpo_override = 0x1f;
  71         popts->write_data_delay = 2;
  72         popts->half_strength_driver_enable = 1;
  73         /* Write leveling override */
  74         popts->wrlvl_en = 1;
  75         popts->wrlvl_override = 1;
  76         popts->wrlvl_sample = 0xf;
  77         popts->wrlvl_start = 0x8;
  78         popts->trwt_override = 1;
  79         popts->trwt = 0;
  80
  81         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  82                 popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
  83                 popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
  84         }
  85 }