1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2013 Freescale Semiconductor, Inc.
8 #include <asm/immap_85xx.h>
9 #include <asm/processor.h>
10 #include <fsl_ddr_sdram.h>
11 #include <fsl_ddr_dimm_params.h>
13 #include <asm/fsl_law.h>
15 /* CONFIG_SYS_DDR_RAW_TIMING */
17 * Hynix H5TQ1G83TFR-H9C
19 dimm_params_t ddr_raw_timing = {
21 .rank_density = 536870912u,
22 .capacity = 536870912u,
23 .primary_sdram_width = 32,
29 .n_banks_per_sdram_device = 8,
31 .burst_lengths_bitmask = 0x0c,
34 .caslat_x = 0x1e << 4, /* 5,6,7,8 */
45 .refresh_rate_ps = 7800000,
49 int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
50 unsigned int controller_number,
51 unsigned int dimm_number)
53 const char dimm_model[] = "Fixed DDR on board";
55 if ((controller_number == 0) && (dimm_number == 0)) {
56 memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
57 memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
58 memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
64 void fsl_ddr_board_options(memctl_options_t *popts,
66 unsigned int ctrl_num)
69 popts->clk_adjust = 6;
70 popts->cpo_override = 0x1f;
71 popts->write_data_delay = 2;
72 popts->half_strength_driver_enable = 1;
73 /* Write leveling override */
75 popts->wrlvl_override = 1;
76 popts->wrlvl_sample = 0xf;
77 popts->wrlvl_start = 0x8;
78 popts->trwt_override = 1;
81 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
82 popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
83 popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;