2 * Copyright 2010-2011 Freescale Semiconductor, Inc.
3 * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
4 * Timur Tabi <timur@freescale.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the Free
8 * Software Foundation; either version 2 of the License, or (at your option)
15 #include <asm/processor.h>
17 #include <asm/cache.h>
18 #include <asm/immap_85xx.h>
19 #include <asm/fsl_pci.h>
20 #include <asm/fsl_ddr_sdram.h>
21 #include <asm/fsl_serdes.h>
24 #include <fdt_support.h>
27 #include <asm/fsl_law.h>
32 #include "../common/ngpixis.h"
34 DECLARE_GLOBAL_DATA_PTR;
36 int board_early_init_f(void)
38 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
40 /* Set pmuxcr to allow both i2c1 and i2c2 */
41 setbits_be32(&gur->pmuxcr, 0x1000);
43 /* Read back the register to synchronize the write. */
44 in_be32(&gur->pmuxcr);
46 /* Set the pin muxing to enable ETSEC2. */
47 clrbits_be32(&gur->pmuxcr2, 0x001F8000);
50 clrsetbits_8(&pixis->brdcfg0, PIXIS_ELBC_SPI_MASK, PIXIS_SPI);
59 printf("Board: P1022DS Sys ID: 0x%02x, "
60 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
61 in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
63 sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
65 switch ((sw & PIXIS_LBMAP_MASK) >> 6) {
67 printf ("vBank: %u\n", ((sw & 0x30) >> 4));
81 #define CONFIG_TFP410_I2C_ADDR 0x38
83 /* Masks for the SSI_TDM and AUDCLK bits of the ngPIXIS BRDCFG1 register. */
84 #define CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK 0x0c
85 #define CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK 0x03
87 /* Route the I2C1 pins to the SSI port instead. */
88 #define CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI 0x08
90 /* Choose the 12.288Mhz codec reference clock */
91 #define CONFIG_PIXIS_BRDCFG1_AUDCLK_12 0x02
93 /* Choose the 11.2896Mhz codec reference clock */
94 #define CONFIG_PIXIS_BRDCFG1_AUDCLK_11 0x01
97 #define CONFIG_PIXIS_BRDCFG0_USB2 0x10
98 /* Connect to TFM bus */
99 #define CONFIG_PIXIS_BRDCFG1_TDM 0x0c
101 #define CONFIG_PIXIS_BRDCFG0_SPI 0x80
103 int misc_init_r(void)
108 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
110 /* For DVI, enable the TFP410 Encoder. */
113 if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0)
115 if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0)
117 debug("DVI Encoder Read: 0x%02x\n", temp);
120 if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0)
122 if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0)
124 debug("DVI Encoder Read: 0x%02x\n",temp);
126 /* Enable the USB2 in PMUXCR2 and FGPA */
127 if (hwconfig("usb2")) {
128 clrsetbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_ETSECUSB_MASK,
129 MPC85xx_PMUXCR2_USB);
130 setbits_8(&pixis->brdcfg0, CONFIG_PIXIS_BRDCFG0_USB2);
133 /* tdm and audio can not enable simultaneous*/
134 if (hwconfig("tdm") && hwconfig("audclk")){
135 printf("WARNING: TDM and AUDIO can not be enabled simultaneous !\n");
139 /* Enable the TDM in PMUXCR and FGPA */
140 if (hwconfig("tdm")) {
141 clrsetbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TDM_MASK,
143 setbits_8(&pixis->brdcfg1, CONFIG_PIXIS_BRDCFG1_TDM);
144 /* TDM need some configration option by SPI */
145 clrsetbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SPI_MASK,
147 setbits_8(&pixis->brdcfg0, CONFIG_PIXIS_BRDCFG0_SPI);
151 * Enable the reference clock for the WM8776 codec, and route the MUX
152 * pins for SSI. The default is the 12.288 MHz clock
155 if (hwconfig("audclk")) {
156 temp = in_8(&pixis->brdcfg1) & ~(CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK |
157 CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK);
158 temp |= CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI;
160 audclk = hwconfig_arg("audclk", &arglen);
161 /* Check the first two chars only */
162 if (audclk && (strncmp(audclk, "11", 2) == 0))
163 temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_11;
165 temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_12;
166 setbits_8(&pixis->brdcfg1, temp);
173 * A list of PCI and SATA slots
186 * This array maps the slot identifiers to their names on the P1022DS board.
188 static const char *slot_names[] = {
189 [SLOT_PCIE1] = "Slot 1",
190 [SLOT_PCIE2] = "Slot 2",
191 [SLOT_PCIE3] = "Slot 3",
192 [SLOT_PCIE4] = "Slot 4",
193 [SLOT_PCIE5] = "Mini-PCIe",
194 [SLOT_SATA1] = "SATA 1",
195 [SLOT_SATA2] = "SATA 2",
199 * This array maps a given SERDES configuration and SERDES device to the PCI or
200 * SATA slot that it connects to. This mapping is hard-coded in the FPGA.
202 static u8 serdes_dev_slot[][SATA2 + 1] = {
203 [0x01] = { [PCIE3] = SLOT_PCIE4, [PCIE2] = SLOT_PCIE5 },
204 [0x02] = { [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
205 [0x09] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE4,
206 [PCIE2] = SLOT_PCIE5 },
207 [0x16] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2,
208 [PCIE2] = SLOT_PCIE3,
209 [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
210 [0x17] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2,
211 [PCIE2] = SLOT_PCIE3 },
212 [0x1a] = { [PCIE1] = SLOT_PCIE1, [PCIE2] = SLOT_PCIE3,
213 [PCIE2] = SLOT_PCIE3,
214 [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
215 [0x1c] = { [PCIE1] = SLOT_PCIE1,
216 [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
217 [0x1e] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE3 },
218 [0x1f] = { [PCIE1] = SLOT_PCIE1 },
223 * Returns the name of the slot to which the PCIe or SATA controller is
226 const char *board_serdes_name(enum srds_prtcl device)
228 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
229 u32 pordevsr = in_be32(&gur->pordevsr);
230 unsigned int srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
231 MPC85xx_PORDEVSR_IO_SEL_SHIFT;
232 enum slot_id slot = serdes_dev_slot[srds_cfg][device];
233 const char *name = slot_names[slot];
242 void pci_init_board(void)
244 fsl_pcie_init_board(0);
248 int board_early_init_r(void)
250 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
251 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
254 * Remap Boot flash + PROMJET region to caching-inhibited
255 * so that flash can be erased properly.
258 /* Flush d-cache and invalidate i-cache of any FLASH data */
262 /* invalidate existing TLB entry for flash + promjet */
263 disable_tlb(flash_esel);
265 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
266 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
267 0, flash_esel, BOOKE_PAGESZ_256M, 1);
273 * Initialize on-board and/or PCI Ethernet devices
277 * 0, no ethernet devices found
278 * >0, number of ethernet devices initialized
280 int board_eth_init(bd_t *bis)
282 struct fsl_pq_mdio_info mdio_info;
283 struct tsec_info_struct tsec_info[2];
284 unsigned int num = 0;
287 SET_STD_TSEC_INFO(tsec_info[num], 1);
291 SET_STD_TSEC_INFO(tsec_info[num], 2);
295 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
296 mdio_info.name = DEFAULT_MII_NAME;
297 fsl_pq_mdio_init(bis, &mdio_info);
299 return tsec_eth_init(bis, tsec_info, num) + pci_eth_init(bis);
302 #ifdef CONFIG_OF_BOARD_SETUP
304 * ft_codec_setup - fix up the clock-frequency property of the codec node
306 * Update the clock-frequency property based on the value of the 'audclk'
307 * hwconfig option. If audclk is not specified, then don't write anything
308 * to the device tree, because it means that the codec clock is disabled.
310 static void ft_codec_setup(void *blob, const char *compatible)
316 audclk = hwconfig_arg("audclk", &arglen);
318 if (strncmp(audclk, "11", 2) == 0)
323 do_fixup_by_compat_u32(blob, compatible, "clock-frequency",
328 void ft_board_setup(void *blob, bd_t *bd)
333 ft_cpu_setup(blob, bd);
335 base = getenv_bootm_low();
336 size = getenv_bootm_size();
338 fdt_fixup_memory(blob, (u64)base, (u64)size);
342 #ifdef CONFIG_FSL_SGMII_RISER
343 fsl_sgmii_riser_fdt_fixup(blob);
346 /* Update the WM8776 node's clock frequency property */
347 ft_codec_setup(blob, "wlf,wm8776");