1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2010-2011 Freescale Semiconductor, Inc.
4 * Authors: Timur Tabi <timur@freescale.com>
6 * FSL DIU Framebuffer driver
10 #include <clock_legacy.h>
13 #include <linux/ctype.h>
15 #include <stdio_dev.h>
17 #include "../common/ngpixis.h"
18 #include <fsl_diu_fb.h>
20 /* The CTL register is called 'csr' in the ngpixis_t structure */
21 #define PX_CTL_ALTACC 0x80
23 #define PX_BRDCFG0_ELBC_SPI_MASK 0xc0
24 #define PX_BRDCFG0_ELBC_SPI_ELBC 0x00
25 #define PX_BRDCFG0_ELBC_SPI_NULL 0xc0
26 #define PX_BRDCFG0_ELBC_DIU 0x02
28 #define PX_BRDCFG1_DVIEN 0x80
29 #define PX_BRDCFG1_DFPEN 0x40
30 #define PX_BRDCFG1_BACKLIGHT 0x20
32 #define PMUXCR_ELBCDIU_MASK 0xc0000000
33 #define PMUXCR_ELBCDIU_NOR16 0x80000000
34 #define PMUXCR_ELBCDIU_DIU 0x40000000
39 * Note that we need to byte-swap the value before it's written to the AD
40 * register. So even though the registers don't look like they're in the same
41 * bit positions as they are on the MPC8610, the same value is written to the
42 * AD register on the MPC8610 and on the P1022.
44 #define AD_BYTE_F 0x10000000
45 #define AD_ALPHA_C_SHIFT 25
46 #define AD_BLUE_C_SHIFT 23
47 #define AD_GREEN_C_SHIFT 21
48 #define AD_RED_C_SHIFT 19
49 #define AD_PIXEL_S_SHIFT 16
50 #define AD_COMP_3_SHIFT 12
51 #define AD_COMP_2_SHIFT 8
52 #define AD_COMP_1_SHIFT 4
53 #define AD_COMP_0_SHIFT 0
56 * Variables used by the DIU/LBC switching code. It's safe to makes these
57 * global, because the DIU requires DDR, so we'll only run this code after
62 static void *lbc_lcs0_ba;
63 static void *lbc_lcs1_ba;
64 static u32 old_br0, old_or0, old_br1, old_or1;
65 static u32 new_br0, new_or0, new_br1, new_or1;
67 void diu_set_pixel_clock(unsigned int pixclock)
69 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
70 unsigned long speed_ccb, temp;
73 speed_ccb = get_bus_freq(0);
74 temp = 1000000000 / pixclock;
76 pixval = speed_ccb / temp;
77 debug("DIU pixval = %u\n", pixval);
79 /* Modify PXCLK in GUTS CLKDVDR */
80 temp = in_be32(&gur->clkdvdr) & 0x2000FFFF;
81 out_be32(&gur->clkdvdr, temp); /* turn off clock */
82 out_be32(&gur->clkdvdr, temp | 0x80000000 | ((pixval & 0x1F) << 16));
85 int platform_diu_init(unsigned int xres, unsigned int yres, const char *port)
87 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
91 phys_addr_t phys0, phys1; /* BR0/BR1 physical addresses */
94 * Indirect mode requires both BR0 and BR1 to be set to "GPCM",
95 * otherwise writes to these addresses won't actually appear on the
96 * local bus, and so the PIXIS won't see them.
98 * In FCM mode, writes go to the NAND controller, which does not pass
99 * them to the localbus directly. So we force BR0 and BR1 into GPCM
100 * mode, since we don't care about what's behind the localbus any
101 * more. However, we save those registers first, so that we can
102 * restore them when necessary.
104 new_br0 = old_br0 = get_lbc_br(0);
105 new_br1 = old_br1 = get_lbc_br(1);
106 new_or0 = old_or0 = get_lbc_or(0);
107 new_or1 = old_or1 = get_lbc_or(1);
110 * Use the existing BRx/ORx values if it's already GPCM. Otherwise,
111 * force the values to simple 32KB GPCM windows with the most
112 * conservative timing.
114 if ((old_br0 & BR_MSEL) != BR_MS_GPCM) {
115 new_br0 = (get_lbc_br(0) & BR_BA) | BR_V;
116 new_or0 = OR_AM_32KB | 0xFF7;
117 set_lbc_br(0, new_br0);
118 set_lbc_or(0, new_or0);
120 if ((old_br1 & BR_MSEL) != BR_MS_GPCM) {
121 new_br1 = (get_lbc_br(1) & BR_BA) | BR_V;
122 new_or1 = OR_AM_32KB | 0xFF7;
123 set_lbc_br(1, new_br1);
124 set_lbc_or(1, new_or1);
128 * Determine the physical addresses for Chip Selects 0 and 1. The
129 * BR0/BR1 registers contain the truncated physical addresses for the
130 * chip selects, mapped via the localbus LAW. Since the BRx registers
131 * only contain the lower 32 bits of the address, we have to determine
132 * the upper 4 bits some other way. The proper way is to scan the LAW
133 * table looking for a matching localbus address. Instead, we cheat.
134 * We know that the upper bits are 0 for 32-bit addressing, or 0xF for
137 #ifdef CONFIG_PHYS_64BIT
138 phys0 = 0xf00000000ULL | (old_br0 & old_or0 & BR_BA);
139 phys1 = 0xf00000000ULL | (old_br1 & old_or1 & BR_BA);
141 phys0 = old_br0 & old_or0 & BR_BA;
142 phys1 = old_br1 & old_or1 & BR_BA;
145 /* Save the LBC LCS0 and LCS1 addresses for the DIU mux functions */
146 lbc_lcs0_ba = map_physmem(phys0, 1, 0);
147 lbc_lcs1_ba = map_physmem(phys1, 1, 0);
149 pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) |
150 (0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) |
151 (2 << AD_RED_C_SHIFT) | (8 << AD_COMP_3_SHIFT) |
152 (8 << AD_COMP_2_SHIFT) | (8 << AD_COMP_1_SHIFT) |
153 (8 << AD_COMP_0_SHIFT) | (3 << AD_PIXEL_S_SHIFT));
155 temp = in_8(&pixis->brdcfg1);
157 if (strncmp(port, "lvds", 4) == 0) {
158 /* Single link LVDS */
159 temp &= ~PX_BRDCFG1_DVIEN;
161 * LVDS also needs backlight enabled, otherwise the display
164 temp |= (PX_BRDCFG1_DFPEN | PX_BRDCFG1_BACKLIGHT);
165 name = "Single-Link LVDS";
167 /* Enable the DVI port, disable the DFP and the backlight */
168 temp &= ~(PX_BRDCFG1_DFPEN | PX_BRDCFG1_BACKLIGHT);
169 temp |= PX_BRDCFG1_DVIEN;
173 printf("DIU: Switching to %s monitor @ %ux%u\n", name, xres, yres);
174 out_8(&pixis->brdcfg1, temp);
177 * Enable PIXIS indirect access mode. This is a hack that allows us to
178 * access PIXIS registers even when the LBC pins have been muxed to the
181 setbits_8(&pixis->csr, PX_CTL_ALTACC);
184 * Route the LAD pins to the DIU. This will disable access to the eLBC,
185 * which means we won't be able to read/write any NOR flash addresses!
187 out_8(lbc_lcs0_ba, offsetof(ngpixis_t, brdcfg0));
188 px_brdcfg0 = in_8(lbc_lcs1_ba);
189 out_8(lbc_lcs1_ba, px_brdcfg0 | PX_BRDCFG0_ELBC_DIU);
192 /* Set PMUXCR to switch the muxed pins from the LBC to the DIU */
193 clrsetbits_be32(&gur->pmuxcr, PMUXCR_ELBCDIU_MASK, PMUXCR_ELBCDIU_DIU);
194 pmuxcr = in_be32(&gur->pmuxcr);
196 return fsl_diu_init(xres, yres, pixel_format, 0);
200 * set_mux_to_lbc - disable the DIU so that we can read/write to elbc
202 * On the Freescale P1022, the DIU video signal and the LBC address/data lines
203 * share the same pins, which means that when the DIU is active (e.g. the
204 * console is on the DVI display), NOR flash cannot be accessed. So we use the
205 * weak accessor feature of the CFI flash code to temporarily switch the pin
206 * mux from DIU to LBC whenever we want to read or write flash. This has a
207 * significant performance penalty, but it's the only way to make it work.
209 * There are two muxes: one on the chip, and one on the board. The chip mux
210 * controls whether the pins are used for the DIU or the LBC, and it is
211 * set via PMUXCR. The board mux controls whether those signals go to
212 * the video connector or the NOR flash chips, and it is set via the ngPIXIS.
214 static int set_mux_to_lbc(void)
216 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
218 /* Switch the muxes only if they're currently set to DIU mode */
219 if ((in_be32(&gur->pmuxcr) & PMUXCR_ELBCDIU_MASK) !=
220 PMUXCR_ELBCDIU_NOR16) {
222 * In DIU mode, the PIXIS can only be accessed indirectly
223 * since we can't read/write the LBC directly.
225 /* Set the board mux to LBC. This will disable the display. */
226 out_8(lbc_lcs0_ba, offsetof(ngpixis_t, brdcfg0));
227 out_8(lbc_lcs1_ba, px_brdcfg0);
230 /* Disable indirect PIXIS mode */
231 out_8(lbc_lcs0_ba, offsetof(ngpixis_t, csr));
232 clrbits_8(lbc_lcs1_ba, PX_CTL_ALTACC);
234 /* Set the chip mux to LBC mode, so that writes go to flash. */
235 out_be32(&gur->pmuxcr, (pmuxcr & ~PMUXCR_ELBCDIU_MASK) |
236 PMUXCR_ELBCDIU_NOR16);
237 in_be32(&gur->pmuxcr);
239 /* Restore the BR0 and BR1 settings */
240 set_lbc_br(0, old_br0);
241 set_lbc_or(0, old_or0);
242 set_lbc_br(1, old_br1);
243 set_lbc_or(1, old_or1);
252 * set_mux_to_diu - re-enable the DIU muxing
254 * This function restores the chip and board muxing to point to the DIU.
256 static void set_mux_to_diu(void)
258 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
260 /* Set BR0 and BR1 to GPCM mode */
261 set_lbc_br(0, new_br0);
262 set_lbc_or(0, new_or0);
263 set_lbc_br(1, new_br1);
264 set_lbc_or(1, new_or1);
266 /* Enable indirect PIXIS mode */
267 setbits_8(&pixis->csr, PX_CTL_ALTACC);
269 /* Set the board mux to DIU. This will enable the display. */
270 out_8(lbc_lcs0_ba, offsetof(ngpixis_t, brdcfg0));
271 out_8(lbc_lcs1_ba, px_brdcfg0 | PX_BRDCFG0_ELBC_DIU);
274 /* Set the chip mux to DIU mode. */
275 out_be32(&gur->pmuxcr, pmuxcr);
276 in_be32(&gur->pmuxcr);
280 * pixis_read - board-specific function to read from the PIXIS
282 * This function overrides the generic pixis_read() function, so that it can
283 * use PIXIS indirect mode if necessary.
285 u8 pixis_read(unsigned int reg)
287 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
289 /* Use indirect mode if the mux is currently set to DIU mode */
290 if ((in_be32(&gur->pmuxcr) & PMUXCR_ELBCDIU_MASK) !=
291 PMUXCR_ELBCDIU_NOR16) {
292 out_8(lbc_lcs0_ba, reg);
293 return in_8(lbc_lcs1_ba);
295 void *p = (void *)PIXIS_BASE;
297 return in_8(p + reg);
302 * pixis_write - board-specific function to write to the PIXIS
304 * This function overrides the generic pixis_write() function, so that it can
305 * use PIXIS indirect mode if necessary.
307 void pixis_write(unsigned int reg, u8 value)
309 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
311 /* Use indirect mode if the mux is currently set to DIU mode */
312 if ((in_be32(&gur->pmuxcr) & PMUXCR_ELBCDIU_MASK) !=
313 PMUXCR_ELBCDIU_NOR16) {
314 out_8(lbc_lcs0_ba, reg);
315 out_8(lbc_lcs1_ba, value);
316 /* Do a read-back to ensure the write completed */
319 void *p = (void *)PIXIS_BASE;
321 out_8(p + reg, value);
325 void pixis_bank_reset(void)
328 * For some reason, a PIXIS bank reset does not work if the PIXIS is
329 * in indirect mode, so switch to direct mode first.
333 out_8(&pixis->vctl, 0);
334 out_8(&pixis->vctl, 1);
339 #ifdef CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
341 void flash_write8(u8 value, void *addr)
343 int sw = set_mux_to_lbc();
345 __raw_writeb(value, addr);
348 * To ensure the post-write is completed to eLBC, software must
349 * perform a dummy read from one valid address from eLBC space
350 * before changing the eLBC_DIU from NOR mode to DIU mode.
351 * set_mux_to_diu() includes a sync that will ensure the
352 * __raw_readb() completes before it switches the mux.
359 void flash_write16(u16 value, void *addr)
361 int sw = set_mux_to_lbc();
363 __raw_writew(value, addr);
366 * To ensure the post-write is completed to eLBC, software must
367 * perform a dummy read from one valid address from eLBC space
368 * before changing the eLBC_DIU from NOR mode to DIU mode.
369 * set_mux_to_diu() includes a sync that will ensure the
370 * __raw_readb() completes before it switches the mux.
377 void flash_write32(u32 value, void *addr)
379 int sw = set_mux_to_lbc();
381 __raw_writel(value, addr);
384 * To ensure the post-write is completed to eLBC, software must
385 * perform a dummy read from one valid address from eLBC space
386 * before changing the eLBC_DIU from NOR mode to DIU mode.
387 * set_mux_to_diu() includes a sync that will ensure the
388 * __raw_readb() completes before it switches the mux.
395 void flash_write64(u64 value, void *addr)
397 int sw = set_mux_to_lbc();
401 * There is no __raw_writeq(), so do the write manually. We don't trust
402 * the compiler, so we use inline assembly.
404 __asm__ __volatile__(
407 : "=m" (*p), "=m" (*(p + 1))
408 : "r" ((uint32_t) (value >> 32)), "r" ((uint32_t) (value)));
412 * To ensure the post-write is completed to eLBC, software must
413 * perform a dummy read from one valid address from eLBC space
414 * before changing the eLBC_DIU from NOR mode to DIU mode. We
415 * read addr+4 because we just wrote to addr+4, so that's how we
416 * maintain execution order. set_mux_to_diu() includes a sync
417 * that will ensure the __raw_readb() completes before it
420 __raw_readb(addr + 4);
425 u8 flash_read8(void *addr)
429 int sw = set_mux_to_lbc();
431 ret = __raw_readb(addr);
438 u16 flash_read16(void *addr)
442 int sw = set_mux_to_lbc();
444 ret = __raw_readw(addr);
451 u32 flash_read32(void *addr)
455 int sw = set_mux_to_lbc();
457 ret = __raw_readl(addr);
464 u64 flash_read64(void *addr)
468 int sw = set_mux_to_lbc();
470 /* There is no __raw_readq(), so do the read manually */
471 ret = *(volatile u64 *)addr;