Merge git://git.denx.de/u-boot-arm
[oweals/u-boot.git] / board / freescale / p1010rdb / tlb.c
1 /*
2  * Copyright 2010-2011 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6
7 #include <common.h>
8 #include <asm/mmu.h>
9
10 struct fsl_e_tlb_entry tlb_table[] = {
11         /* TLB 0 - for temp stack in cache */
12         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
13                         MAS3_SX|MAS3_SW|MAS3_SR, 0,
14                         0, 0, BOOKE_PAGESZ_4K, 0),
15         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
16                         CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
17                         MAS3_SX|MAS3_SW|MAS3_SR, 0,
18                         0, 0, BOOKE_PAGESZ_4K, 0),
19         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
20                         CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
21                         MAS3_SX|MAS3_SW|MAS3_SR, 0,
22                         0, 0, BOOKE_PAGESZ_4K, 0),
23         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
24                         CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
25                         MAS3_SX|MAS3_SW|MAS3_SR, 0,
26                         0, 0, BOOKE_PAGESZ_4K, 0),
27
28         /* TLB 1 */
29         /* *I*** - Covers boot page */
30         SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
31                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
32                       0, 0, BOOKE_PAGESZ_4K, 1),
33 #ifdef CONFIG_SPL_NAND_MINIMAL
34         SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000,
35                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
36                       0, 10, BOOKE_PAGESZ_4K, 1),
37 #endif
38
39         /* *I*G* - CCSRBAR */
40         SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
41                         MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
42                         0, 1, BOOKE_PAGESZ_1M, 1),
43
44 #ifndef CONFIG_SPL_BUILD
45 #ifndef CONFIG_SDCARD
46         SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
47                         MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
48                         0, 2, BOOKE_PAGESZ_16M, 1),
49
50         SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x1000000,
51                         CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000,
52                         MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
53                         0, 3, BOOKE_PAGESZ_16M, 1),
54 #endif
55
56 #ifdef CONFIG_PCI
57         /* *I*G* - PCI */
58         SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
59                         MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
60                         0, 4, BOOKE_PAGESZ_1G, 1),
61
62         /* *I*G* - PCI I/O */
63         SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
64                         MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
65                         0, 5, BOOKE_PAGESZ_256K, 1),
66 #endif
67 #endif
68
69 #ifndef CONFIG_SDCARD
70         /* *I*G - Board CPLD  */
71         SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
72                         MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
73                         0, 6, BOOKE_PAGESZ_256K, 1),
74
75         SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
76                         MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
77                         0, 7, BOOKE_PAGESZ_1M, 1),
78 #endif
79
80 #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
81         SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
82                         MAS3_SX|MAS3_SW|MAS3_SR, 0,
83                         0, 8, BOOKE_PAGESZ_1G, 1)
84 #endif
85 };
86
87 int num_tlb_entries = ARRAY_SIZE(tlb_table);