board/freescale/p1010rdb/p1010rdb.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2010-2011 Freescale Semiconductor, Inc.
   4  * Copyright 2020 NXP
   5  */
   6
   7 #include <common.h>
   8 #include <init.h>
   9 #include <net.h>
  10 #include <asm/processor.h>
  11 #include <asm/mmu.h>
  12 #include <asm/cache.h>
  13 #include <asm/immap_85xx.h>
  14 #include <asm/io.h>
  15 #include <env.h>
  16 #include <miiphy.h>
  17 #include <linux/libfdt.h>
  18 #include <fdt_support.h>
  19 #include <fsl_mdio.h>
  20 #include <tsec.h>
  21 #include <mmc.h>
  22 #include <netdev.h>
  23 #include <pci.h>
  24 #include <asm/fsl_serdes.h>
  25 #include <fsl_ifc.h>
  26 #include <asm/fsl_pci.h>
  27 #include <hwconfig.h>
  28 #include <i2c.h>
  29
  30 DECLARE_GLOBAL_DATA_PTR;
  31
  32 #define GPIO4_PCIE_RESET_SET            0x08000000
  33 #define MUX_CPLD_CAN_UART               0x00
  34 #define MUX_CPLD_TDM                    0x01
  35 #define MUX_CPLD_SPICS0_FLASH           0x00
  36 #define MUX_CPLD_SPICS0_SLIC            0x02
  37 #define PMUXCR1_IFC_MASK       0x00ffff00
  38 #define PMUXCR1_SDHC_MASK      0x00fff000
  39 #define PMUXCR1_SDHC_ENABLE    0x00555000
  40
  41 enum {
  42         MUX_TYPE_IFC,
  43         MUX_TYPE_SDHC,
  44         MUX_TYPE_SPIFLASH,
  45         MUX_TYPE_TDM,
  46         MUX_TYPE_CAN,
  47         MUX_TYPE_CS0_NOR,
  48         MUX_TYPE_CS0_NAND,
  49 };
  50
  51 enum {
  52         I2C_READ_BANK,
  53         I2C_READ_PCB_VER,
  54 };
  55
  56 static uint sd_ifc_mux;
  57
  58 struct cpld_data {
  59         u8 cpld_ver; /* cpld revision */
  60 #if defined(CONFIG_TARGET_P1010RDB_PA)
  61         u8 pcba_ver; /* pcb revision number */
  62         u8 twindie_ddr3;
  63         u8 res1[6];
  64         u8 bank_sel; /* NOR Flash bank */
  65         u8 res2[5];
  66         u8 usb2_sel;
  67         u8 res3[1];
  68         u8 porsw_sel;
  69         u8 tdm_can_sel;
  70         u8 spi_cs0_sel; /* SPI CS0 SLIC/SPI Flash */
  71         u8 por0; /* POR Options */
  72         u8 por1; /* POR Options */
  73         u8 por2; /* POR Options */
  74         u8 por3; /* POR Options */
  75 #elif defined(CONFIG_TARGET_P1010RDB_PB)
  76         u8 rom_loc;
  77 #endif
  78 };
  79
  80 int board_early_init_f(void)
  81 {
  82         ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
  83         struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
  84         /* Clock configuration to access CPLD using IFC(GPCM) */
  85         setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
  86         /*
  87         * Reset PCIe slots via GPIO4
  88         */
  89         setbits_be32(&pgpio->gpdir, GPIO4_PCIE_RESET_SET);
  90         setbits_be32(&pgpio->gpdat, GPIO4_PCIE_RESET_SET);
  91
  92         return 0;
  93 }
  94
  95 int board_early_init_r(void)
  96 {
  97         const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
  98         int flash_esel = find_tlb_idx((void *)flashbase, 1);
  99
 100         /*
 101          * Remap Boot flash region to caching-inhibited
 102          * so that flash can be erased properly.
 103          */
 104
 105         /* Flush d-cache and invalidate i-cache of any FLASH data */
 106         flush_dcache();
 107         invalidate_icache();
 108
 109         if (flash_esel == -1) {
 110                 /* very unlikely unless something is messed up */
 111                 puts("Error: Could not find TLB for FLASH BASE\n");
 112                 flash_esel = 2; /* give our best effort to continue */
 113         } else {
 114                 /* invalidate existing TLB entry for flash */
 115                 disable_tlb(flash_esel);
 116         }
 117
 118         set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
 119                         MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 120                         0, flash_esel, BOOKE_PAGESZ_16M, 1);
 121
 122         set_tlb(1, flashbase + 0x1000000,
 123                         CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000,
 124                         MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 125                         0, flash_esel+1, BOOKE_PAGESZ_16M, 1);
 126         return 0;
 127 }
 128
 129 #if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI)
 130 void pci_init_board(void)
 131 {
 132         fsl_pcie_init_board(0);
 133 }
 134 #endif /* ifdef CONFIG_PCI */
 135
 136 int config_board_mux(int ctrl_type)
 137 {
 138         ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 139         u8 tmp;
 140
 141 #ifdef CONFIG_DM_I2C
 142         struct udevice *dev;
 143         int ret;
 144 #if defined(CONFIG_TARGET_P1010RDB_PA)
 145         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 146
 147         ret = i2c_get_chip_for_busnum(I2C_PCA9557_BUS_NUM,
 148                                       I2C_PCA9557_ADDR1, 1, &dev);
 149         if (ret) {
 150                 printf("%s: Cannot find udev for a bus %d\n",
 151                        __func__, I2C_PCA9557_BUS_NUM);
 152                 return ret;
 153         }
 154         switch (ctrl_type) {
 155         case MUX_TYPE_IFC:
 156                 tmp = 0xf0;
 157                 dm_i2c_write(dev, 3, &tmp, 1);
 158                 tmp = 0x01;
 159                 dm_i2c_write(dev, 1, &tmp, 1);
 160                 sd_ifc_mux = MUX_TYPE_IFC;
 161                 clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);
 162                 break;
 163         case MUX_TYPE_SDHC:
 164                 tmp = 0xf0;
 165                 dm_i2c_write(dev, 3, &tmp, 1);
 166                 tmp = 0x05;
 167                 dm_i2c_write(dev, 1, &tmp, 1);
 168                 sd_ifc_mux = MUX_TYPE_SDHC;
 169                 clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,
 170                                 PMUXCR1_SDHC_ENABLE);
 171                 break;
 172         case MUX_TYPE_SPIFLASH:
 173                 out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_FLASH);
 174                 break;
 175         case MUX_TYPE_TDM:
 176                 out_8(&cpld_data->tdm_can_sel, MUX_CPLD_TDM);
 177                 out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_SLIC);
 178                 break;
 179         case MUX_TYPE_CAN:
 180                 out_8(&cpld_data->tdm_can_sel, MUX_CPLD_CAN_UART);
 181                 break;
 182         default:
 183                 break;
 184         }
 185 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 186         ret = i2c_get_chip_for_busnum(I2C_PCA9557_BUS_NUM,
 187                                       I2C_PCA9557_ADDR2, 1, &dev);
 188         if (ret) {
 189                 printf("%s: Cannot find udev for a bus %d\n",
 190                        __func__, I2C_PCA9557_BUS_NUM);
 191                 return ret;
 192         }
 193         switch (ctrl_type) {
 194         case MUX_TYPE_IFC:
 195                 dm_i2c_read(dev, 0, &tmp, 1);
 196                 clrbits_8(&tmp, 0x04);
 197                 dm_i2c_write(dev, 1, &tmp, 1);
 198                 dm_i2c_read(dev, 3, &tmp, 1);
 199                 clrbits_8(&tmp, 0x04);
 200                 dm_i2c_write(dev, 3, &tmp, 1);
 201                 sd_ifc_mux = MUX_TYPE_IFC;
 202                 clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);
 203                 break;
 204         case MUX_TYPE_SDHC:
 205                 dm_i2c_read(dev, 0, &tmp, 1);
 206                 setbits_8(&tmp, 0x04);
 207                 dm_i2c_write(dev, 1, &tmp, 1);
 208                 dm_i2c_read(dev, 3, &tmp, 1);
 209                 clrbits_8(&tmp, 0x04);
 210                 dm_i2c_write(dev, 3, &tmp, 1);
 211                 sd_ifc_mux = MUX_TYPE_SDHC;
 212                 clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,
 213                                 PMUXCR1_SDHC_ENABLE);
 214                 break;
 215         case MUX_TYPE_SPIFLASH:
 216                 dm_i2c_read(dev, 0, &tmp, 1);
 217                 clrbits_8(&tmp, 0x80);
 218                 dm_i2c_write(dev, 1, &tmp, 1);
 219                 dm_i2c_read(dev, 3, &tmp, 1);
 220                 clrbits_8(&tmp, 0x80);
 221                 dm_i2c_write(dev, 3, &tmp, 1);
 222                 break;
 223         case MUX_TYPE_TDM:
 224                 dm_i2c_read(dev, 0, &tmp, 1);
 225                 setbits_8(&tmp, 0x82);
 226                 dm_i2c_write(dev, 1, &tmp, 1);
 227                 dm_i2c_read(dev, 3, &tmp, 1);
 228                 clrbits_8(&tmp, 0x82);
 229                 dm_i2c_write(dev, 3, &tmp, 1);
 230                 break;
 231         case MUX_TYPE_CAN:
 232                 dm_i2c_read(dev, 0, &tmp, 1);
 233                 clrbits_8(&tmp, 0x02);
 234                 dm_i2c_write(dev, 1, &tmp, 1);
 235                 dm_i2c_read(dev, 3, &tmp, 1);
 236                 clrbits_8(&tmp, 0x02);
 237                 dm_i2c_write(dev, 3, &tmp, 1);
 238                 break;
 239         case MUX_TYPE_CS0_NOR:
 240                 dm_i2c_read(dev, 0, &tmp, 1);
 241                 clrbits_8(&tmp, 0x08);
 242                 dm_i2c_write(dev, 1, &tmp, 1);
 243                 dm_i2c_read(dev, 3, &tmp, 1);
 244                 clrbits_8(&tmp, 0x08);
 245                 dm_i2c_write(dev, 3, &tmp, 1);
 246                 break;
 247         case MUX_TYPE_CS0_NAND:
 248                 dm_i2c_read(dev, 0, &tmp, 1);
 249                 setbits_8(&tmp, 0x08);
 250                 dm_i2c_write(dev, 1, &tmp, 1);
 251                 dm_i2c_read(dev, 3, &tmp, 1);
 252                 clrbits_8(&tmp, 0x08);
 253                 dm_i2c_write(dev, 3, &tmp, 1);
 254                 break;
 255         default:
 256                 break;
 257         }
 258 #endif
 259 #else
 260 #if defined(CONFIG_TARGET_P1010RDB_PA)
 261         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 262
 263         switch (ctrl_type) {
 264         case MUX_TYPE_IFC:
 265                 i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
 266                 tmp = 0xf0;
 267                 i2c_write(I2C_PCA9557_ADDR1, 3, 1, &tmp, 1);
 268                 tmp = 0x01;
 269                 i2c_write(I2C_PCA9557_ADDR1, 1, 1, &tmp, 1);
 270                 sd_ifc_mux = MUX_TYPE_IFC;
 271                 clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);
 272                 break;
 273         case MUX_TYPE_SDHC:
 274                 i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
 275                 tmp = 0xf0;
 276                 i2c_write(I2C_PCA9557_ADDR1, 3, 1, &tmp, 1);
 277                 tmp = 0x05;
 278                 i2c_write(I2C_PCA9557_ADDR1, 1, 1, &tmp, 1);
 279                 sd_ifc_mux = MUX_TYPE_SDHC;
 280                 clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,
 281                                 PMUXCR1_SDHC_ENABLE);
 282                 break;
 283         case MUX_TYPE_SPIFLASH:
 284                 out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_FLASH);
 285                 break;
 286         case MUX_TYPE_TDM:
 287                 out_8(&cpld_data->tdm_can_sel, MUX_CPLD_TDM);
 288                 out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_SLIC);
 289                 break;
 290         case MUX_TYPE_CAN:
 291                 out_8(&cpld_data->tdm_can_sel, MUX_CPLD_CAN_UART);
 292                 break;
 293         default:
 294                 break;
 295         }
 296 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 297         uint orig_bus = i2c_get_bus_num();
 298         i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
 299
 300         switch (ctrl_type) {
 301         case MUX_TYPE_IFC:
 302                 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
 303                 clrbits_8(&tmp, 0x04);
 304                 i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
 305                 i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
 306                 clrbits_8(&tmp, 0x04);
 307                 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
 308                 sd_ifc_mux = MUX_TYPE_IFC;
 309                 clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);
 310                 break;
 311         case MUX_TYPE_SDHC:
 312                 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
 313                 setbits_8(&tmp, 0x04);
 314                 i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
 315                 i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
 316                 clrbits_8(&tmp, 0x04);
 317                 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
 318                 sd_ifc_mux = MUX_TYPE_SDHC;
 319                 clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,
 320                                 PMUXCR1_SDHC_ENABLE);
 321                 break;
 322         case MUX_TYPE_SPIFLASH:
 323                 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
 324                 clrbits_8(&tmp, 0x80);
 325                 i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
 326                 i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
 327                 clrbits_8(&tmp, 0x80);
 328                 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
 329                 break;
 330         case MUX_TYPE_TDM:
 331                 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
 332                 setbits_8(&tmp, 0x82);
 333                 i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
 334                 i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
 335                 clrbits_8(&tmp, 0x82);
 336                 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
 337                 break;
 338         case MUX_TYPE_CAN:
 339                 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
 340                 clrbits_8(&tmp, 0x02);
 341                 i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
 342                 i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
 343                 clrbits_8(&tmp, 0x02);
 344                 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
 345                 break;
 346         case MUX_TYPE_CS0_NOR:
 347                 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
 348                 clrbits_8(&tmp, 0x08);
 349                 i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
 350                 i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
 351                 clrbits_8(&tmp, 0x08);
 352                 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
 353                 break;
 354         case MUX_TYPE_CS0_NAND:
 355                 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
 356                 setbits_8(&tmp, 0x08);
 357                 i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
 358                 i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
 359                 clrbits_8(&tmp, 0x08);
 360                 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
 361                 break;
 362         default:
 363                 break;
 364         }
 365         i2c_set_bus_num(orig_bus);
 366 #endif
 367 #endif
 368         return 0;
 369 }
 370
 371 #ifdef CONFIG_TARGET_P1010RDB_PB
 372 int i2c_pca9557_read(int type)
 373 {
 374         u8 val;
 375         int bus_num = I2C_PCA9557_BUS_NUM;
 376
 377 #ifdef CONFIG_DM_I2C
 378         struct udevice *dev;
 379         int ret;
 380
 381         ret = i2c_get_chip_for_busnum(bus_num, I2C_PCA9557_ADDR2, 1, &dev);
 382         if (ret) {
 383                 printf("%s: Cannot find udev for a bus %d\n",
 384                        __func__, bus_num);
 385                 return ret;
 386         }
 387         dm_i2c_read(dev, 0, &val, 1);
 388 #else
 389         i2c_set_bus_num(bus_num);
 390         i2c_read(I2C_PCA9557_ADDR2, 0, 1, &val, 1);
 391 #endif
 392
 393         switch (type) {
 394         case I2C_READ_BANK:
 395                 val = (val & 0x10) >> 4;
 396                 break;
 397         case I2C_READ_PCB_VER:
 398                 val = ((val & 0x60) >> 5) + 1;
 399                 break;
 400         default:
 401                 break;
 402         }
 403
 404         return val;
 405 }
 406 #endif
 407
 408 int checkboard(void)
 409 {
 410         struct cpu_type *cpu;
 411         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 412         u8 val;
 413
 414         cpu = gd->arch.cpu;
 415 #if defined(CONFIG_TARGET_P1010RDB_PA)
 416         printf("Board: %sRDB-PA, ", cpu->name);
 417 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 418         printf("Board: %sRDB-PB, ", cpu->name);
 419 #ifdef CONFIG_DM_I2C
 420         struct udevice *dev;
 421         int ret;
 422
 423         ret = i2c_get_chip_for_busnum(I2C_PCA9557_BUS_NUM, I2C_PCA9557_ADDR2,
 424                                       1, &dev);
 425         if (ret) {
 426                 printf("%s: Cannot find udev for a bus %d\n", __func__,
 427                        I2C_PCA9557_BUS_NUM);
 428                 return ret;
 429         }
 430         val = 0x0;  /* no polarity inversion */
 431         dm_i2c_write(dev, 2, &val, 1);
 432 #else
 433         i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
 434         i2c_init(CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE);
 435         val = 0x0;  /* no polarity inversion */
 436         i2c_write(I2C_PCA9557_ADDR2, 2, 1, &val, 1);
 437 #endif
 438 #endif
 439
 440 #ifdef CONFIG_SDCARD
 441         /* switch to IFC to read info from CPLD */
 442         config_board_mux(MUX_TYPE_IFC);
 443 #endif
 444
 445 #if defined(CONFIG_TARGET_P1010RDB_PA)
 446         val = (in_8(&cpld_data->pcba_ver) & 0xf);
 447         printf("PCB: v%x.0\n", val);
 448 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 449         val = in_8(&cpld_data->cpld_ver);
 450         printf("CPLD: v%x.%x, ", val >> 4, val & 0xf);
 451         printf("PCB: v%x.0, ", i2c_pca9557_read(I2C_READ_PCB_VER));
 452         val = in_8(&cpld_data->rom_loc) & 0xf;
 453         puts("Boot from: ");
 454         switch (val) {
 455         case 0xf:
 456                 config_board_mux(MUX_TYPE_CS0_NOR);
 457                 printf("NOR vBank%d\n", i2c_pca9557_read(I2C_READ_BANK));
 458                 break;
 459         case 0xe:
 460                 puts("SDHC\n");
 461                 val = 0x60; /* set pca9557 pin input/output */
 462 #ifdef CONFIG_DM_I2C
 463                 dm_i2c_write(dev, 3, &val, 1);
 464 #else
 465                 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &val, 1);
 466 #endif
 467                 break;
 468         case 0x5:
 469                 config_board_mux(MUX_TYPE_IFC);
 470                 config_board_mux(MUX_TYPE_CS0_NAND);
 471                 puts("NAND\n");
 472                 break;
 473         case 0x6:
 474                 config_board_mux(MUX_TYPE_IFC);
 475                 puts("SPI\n");
 476                 break;
 477         default:
 478                 puts("unknown\n");
 479                 break;
 480         }
 481 #endif
 482         return 0;
 483 }
 484
 485 int board_eth_init(bd_t *bis)
 486 {
 487 #ifdef CONFIG_TSEC_ENET
 488         struct fsl_pq_mdio_info mdio_info;
 489         struct tsec_info_struct tsec_info[4];
 490         struct cpu_type *cpu;
 491         int num = 0;
 492
 493         cpu = gd->arch.cpu;
 494
 495 #ifdef CONFIG_TSEC1
 496         SET_STD_TSEC_INFO(tsec_info[num], 1);
 497         num++;
 498 #endif
 499 #ifdef CONFIG_TSEC2
 500         SET_STD_TSEC_INFO(tsec_info[num], 2);
 501         num++;
 502 #endif
 503 #ifdef CONFIG_TSEC3
 504         /* P1014 and it's derivatives do not support eTSEC3 */
 505         if (cpu->soc_ver != SVR_P1014) {
 506                 SET_STD_TSEC_INFO(tsec_info[num], 3);
 507                 num++;
 508         }
 509 #endif
 510         if (!num) {
 511                 printf("No TSECs initialized\n");
 512                 return 0;
 513         }
 514
 515         mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
 516         mdio_info.name = DEFAULT_MII_NAME;
 517
 518         fsl_pq_mdio_init(bis, &mdio_info);
 519
 520         tsec_eth_init(bis, tsec_info, num);
 521 #endif
 522
 523         return pci_eth_init(bis);
 524 }
 525
 526 #if defined(CONFIG_OF_BOARD_SETUP)
 527 void fdt_del_flexcan(void *blob)
 528 {
 529         int nodeoff = 0;
 530
 531         while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
 532                                 "fsl,p1010-flexcan")) >= 0) {
 533                 fdt_del_node(blob, nodeoff);
 534         }
 535 }
 536
 537 void fdt_del_spi_flash(void *blob)
 538 {
 539         int nodeoff = 0;
 540
 541         while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
 542                                 "spansion,s25sl12801")) >= 0) {
 543                 fdt_del_node(blob, nodeoff);
 544         }
 545 }
 546
 547 void fdt_del_spi_slic(void *blob)
 548 {
 549         int nodeoff = 0;
 550
 551         while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
 552                                 "zarlink,le88266")) >= 0) {
 553                 fdt_del_node(blob, nodeoff);
 554         }
 555 }
 556
 557 void fdt_del_tdm(void *blob)
 558 {
 559         int nodeoff = 0;
 560
 561         while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
 562                                 "fsl,starlite-tdm")) >= 0) {
 563                 fdt_del_node(blob, nodeoff);
 564         }
 565 }
 566
 567 void fdt_del_sdhc(void *blob)
 568 {
 569         int nodeoff = 0;
 570
 571         while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
 572                         "fsl,esdhc")) >= 0) {
 573                 fdt_del_node(blob, nodeoff);
 574         }
 575 }
 576
 577 void fdt_del_ifc(void *blob)
 578 {
 579         int nodeoff = 0;
 580
 581         while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
 582                                 "fsl,ifc")) >= 0) {
 583                 fdt_del_node(blob, nodeoff);
 584         }
 585 }
 586
 587 void fdt_disable_uart1(void *blob)
 588 {
 589         int nodeoff;
 590
 591         nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,ns16550",
 592                                         CONFIG_SYS_NS16550_COM2);
 593
 594         if (nodeoff > 0) {
 595                 fdt_status_disabled(blob, nodeoff);
 596         } else {
 597                 printf("WARNING unable to set status for fsl,ns16550 "
 598                         "uart1: %s\n", fdt_strerror(nodeoff));
 599         }
 600 }
 601
 602 int ft_board_setup(void *blob, bd_t *bd)
 603 {
 604         phys_addr_t base;
 605         phys_size_t size;
 606         struct cpu_type *cpu;
 607
 608         cpu = gd->arch.cpu;
 609
 610         ft_cpu_setup(blob, bd);
 611
 612         base = env_get_bootm_low();
 613         size = env_get_bootm_size();
 614
 615 #if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI)
 616         FT_FSL_PCI_SETUP;
 617 #endif
 618
 619         fdt_fixup_memory(blob, (u64)base, (u64)size);
 620
 621 #if defined(CONFIG_HAS_FSL_DR_USB)
 622         fsl_fdt_fixup_dr_usb(blob, bd);
 623 #endif
 624
 625        /* P1014 and it's derivatives don't support CAN and eTSEC3 */
 626         if (cpu->soc_ver == SVR_P1014) {
 627                 fdt_del_flexcan(blob);
 628                 fdt_del_node_and_alias(blob, "ethernet2");
 629         }
 630
 631         /* Delete IFC node as IFC pins are multiplexing with SDHC */
 632         if (sd_ifc_mux != MUX_TYPE_IFC)
 633                 fdt_del_ifc(blob);
 634         else
 635                 fdt_del_sdhc(blob);
 636
 637         if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) {
 638                 fdt_del_tdm(blob);
 639                 fdt_del_spi_slic(blob);
 640         } else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) {
 641                 fdt_del_flexcan(blob);
 642                 fdt_del_spi_flash(blob);
 643                 fdt_disable_uart1(blob);
 644         } else {
 645                 /*
 646                  * If we don't set fsl_p1010mux:tdm_can to "can" or "tdm"
 647                  * explicitly, defaultly spi_cs_sel to spi-flash instead of
 648                  * to tdm/slic.
 649                  */
 650                 fdt_del_tdm(blob);
 651                 fdt_del_flexcan(blob);
 652                 fdt_disable_uart1(blob);
 653         }
 654
 655         return 0;
 656 }
 657 #endif
 658
 659 #ifdef CONFIG_SDCARD
 660 int board_mmc_init(bd_t *bis)
 661 {
 662         config_board_mux(MUX_TYPE_SDHC);
 663                 return -1;
 664 }
 665 #else
 666 void board_reset(void)
 667 {
 668         /* mux to IFC to enable CPLD for reset */
 669         if (sd_ifc_mux != MUX_TYPE_IFC)
 670                 config_board_mux(MUX_TYPE_IFC);
 671 }
 672 #endif
 673
 674
 675 int misc_init_r(void)
 676 {
 677         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 678
 679         if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) {
 680                 clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN1_TDM |
 681                                 MPC85xx_PMUXCR_CAN1_UART |
 682                                 MPC85xx_PMUXCR_CAN2_TDM |
 683                                 MPC85xx_PMUXCR_CAN2_UART);
 684                 config_board_mux(MUX_TYPE_CAN);
 685         } else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) {
 686                 clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_UART |
 687                                 MPC85xx_PMUXCR_CAN1_UART);
 688                 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_TDM |
 689                                 MPC85xx_PMUXCR_CAN1_TDM);
 690                 clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_GPIO);
 691                 setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_TDM);
 692                 config_board_mux(MUX_TYPE_TDM);
 693         } else {
 694                 /* defaultly spi_cs_sel to flash */
 695                 config_board_mux(MUX_TYPE_SPIFLASH);
 696         }
 697
 698         if (hwconfig("esdhc"))
 699                 config_board_mux(MUX_TYPE_SDHC);
 700         else if (hwconfig("ifc"))
 701                 config_board_mux(MUX_TYPE_IFC);
 702
 703 #ifdef CONFIG_TARGET_P1010RDB_PB
 704         setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_GPIO01_DRVVBUS);
 705 #endif
 706         return 0;
 707 }
 708
 709 #ifndef CONFIG_SPL_BUILD
 710 static int pin_mux_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
 711                                 char * const argv[])
 712 {
 713         if (argc < 2)
 714                 return CMD_RET_USAGE;
 715         if (strcmp(argv[1], "ifc") == 0)
 716                 config_board_mux(MUX_TYPE_IFC);
 717         else if (strcmp(argv[1], "sdhc") == 0)
 718                 config_board_mux(MUX_TYPE_SDHC);
 719         else
 720                 return CMD_RET_USAGE;
 721         return 0;
 722 }
 723
 724 U_BOOT_CMD(
 725         mux, 2, 0, pin_mux_cmd,
 726         "configure multiplexing pin for IFC/SDHC bus in runtime",
 727         "bus_type (e.g. mux sdhc)"
 728 );
 729 #endif