2 * Copyright (C) 2015 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
7 #include <asm/arch/clock.h>
8 #include <asm/arch/imx-regs.h>
9 #include <asm/arch/mx7-pins.h>
10 #include <asm/arch/sys_proto.h>
12 #include <asm/imx-common/iomux-v3.h>
14 #include <linux/sizes.h>
16 #include <fsl_esdhc.h>
20 #include <power/pmic.h>
21 #include <power/pfuze3000_pmic.h>
22 #include "../common/pfuze.h"
24 #include <asm/imx-common/mxc_i2c.h>
25 #include <asm/arch/crm_regs.h>
27 #include <usb/ehci-ci.h>
29 DECLARE_GLOBAL_DATA_PTR;
31 #define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
32 PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
34 #define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
35 PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
37 #define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
38 #define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM)
40 #define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
42 #define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
43 PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM)
45 #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
46 PAD_CTL_DSE_3P3V_49OHM)
48 #define QSPI_PAD_CTRL \
49 (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
51 #define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
53 #define SPI_PAD_CTRL \
54 (PAD_CTL_HYS | PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_FAST)
56 #define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM)
57 #ifdef CONFIG_SYS_I2C_MXC
58 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
60 static struct i2c_pads_info i2c_pad_info1 = {
62 .i2c_mode = MX7D_PAD_I2C1_SCL__I2C1_SCL | PC,
63 .gpio_mode = MX7D_PAD_I2C1_SCL__GPIO4_IO8 | PC,
64 .gp = IMX_GPIO_NR(4, 8),
67 .i2c_mode = MX7D_PAD_I2C1_SDA__I2C1_SDA | PC,
68 .gpio_mode = MX7D_PAD_I2C1_SDA__GPIO4_IO9 | PC,
69 .gp = IMX_GPIO_NR(4, 9),
74 static iomux_v3_cfg_t const ecspi3_pads[] = {
75 MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
76 MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
77 MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
78 MX7D_PAD_SAI2_TX_DATA__GPIO6_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
81 int board_spi_cs_gpio(unsigned bus, unsigned cs)
83 return (bus == 2 && cs == 0) ? (IMX_GPIO_NR(6, 22)) : -1;
86 static void setup_spi(void)
88 imx_iomux_v3_setup_multiple_pads(ecspi3_pads, ARRAY_SIZE(ecspi3_pads));
93 gd->ram_size = PHYS_SDRAM_SIZE;
98 static iomux_v3_cfg_t const wdog_pads[] = {
99 MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),
102 static iomux_v3_cfg_t const uart1_pads[] = {
103 MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
104 MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
107 static iomux_v3_cfg_t const usdhc1_pads[] = {
108 MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
109 MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
110 MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
111 MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
112 MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
113 MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
115 MX7D_PAD_SD1_CD_B__GPIO5_IO0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
116 MX7D_PAD_SD1_RESET_B__GPIO5_IO2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
119 static iomux_v3_cfg_t const usdhc3_emmc_pads[] = {
120 MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
121 MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
122 MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
123 MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
124 MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
125 MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
126 MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
127 MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
128 MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
129 MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
130 MX7D_PAD_SD3_STROBE__SD3_STROBE | MUX_PAD_CTRL(USDHC_PAD_CTRL),
132 MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
135 static iomux_v3_cfg_t const usb_otg1_pads[] = {
136 MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
139 static iomux_v3_cfg_t const usb_otg2_pads[] = {
140 MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
143 #define IOX_SDI IMX_GPIO_NR(1, 9)
144 #define IOX_STCP IMX_GPIO_NR(1, 12)
145 #define IOX_SHCP IMX_GPIO_NR(1, 13)
147 static iomux_v3_cfg_t const iox_pads[] = {
149 MX7D_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL),
151 MX7D_PAD_GPIO1_IO12__GPIO1_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
153 MX7D_PAD_GPIO1_IO13__GPIO1_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL),
161 * SENSOR_RST_B --> Q4
188 static enum qn_level seq[3][2] = {
189 {0, 1}, {1, 1}, {0, 0}
192 static enum qn_func qn_output[8] = {
193 qn_disable, qn_reset, qn_reset, qn_reset, qn_reset, qn_reset, qn_enable,
197 static void iox74lv_init(void)
201 for (i = 7; i >= 0; i--) {
202 gpio_direction_output(IOX_SHCP, 0);
203 gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]);
205 gpio_direction_output(IOX_SHCP, 1);
209 gpio_direction_output(IOX_STCP, 0);
212 * shift register will be output to pins
214 gpio_direction_output(IOX_STCP, 1);
216 for (i = 7; i >= 0; i--) {
217 gpio_direction_output(IOX_SHCP, 0);
218 gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]);
220 gpio_direction_output(IOX_SHCP, 1);
223 gpio_direction_output(IOX_STCP, 0);
226 * shift register will be output to pins
228 gpio_direction_output(IOX_STCP, 1);
231 #ifdef CONFIG_NAND_MXS
232 static iomux_v3_cfg_t const gpmi_pads[] = {
233 MX7D_PAD_SD3_DATA0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
234 MX7D_PAD_SD3_DATA1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
235 MX7D_PAD_SD3_DATA2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
236 MX7D_PAD_SD3_DATA3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
237 MX7D_PAD_SD3_DATA4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
238 MX7D_PAD_SD3_DATA5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL),
239 MX7D_PAD_SD3_DATA6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL),
240 MX7D_PAD_SD3_DATA7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL),
241 MX7D_PAD_SD3_CLK__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL),
242 MX7D_PAD_SD3_CMD__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL),
243 MX7D_PAD_SD3_STROBE__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
244 MX7D_PAD_SD3_RESET_B__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
245 MX7D_PAD_SAI1_MCLK__NAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
246 MX7D_PAD_SAI1_RX_BCLK__NAND_CE3_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
247 MX7D_PAD_SAI1_RX_SYNC__NAND_CE2_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
248 MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
249 MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
250 MX7D_PAD_SAI1_TX_SYNC__NAND_DQS | MUX_PAD_CTRL(NAND_PAD_CTRL),
251 MX7D_PAD_SAI1_TX_DATA__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL),
254 static void setup_gpmi_nand(void)
256 imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
258 /* NAND_USDHC_BUS_CLK is set in rom */
263 #ifdef CONFIG_VIDEO_MXS
264 static iomux_v3_cfg_t const lcd_pads[] = {
265 MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
266 MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
267 MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
268 MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
269 MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL),
270 MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL),
271 MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL),
272 MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL),
273 MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
274 MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL),
275 MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL),
276 MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL),
277 MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL),
278 MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL),
279 MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
280 MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
281 MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
282 MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
283 MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
284 MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
285 MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
286 MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
287 MX7D_PAD_LCD_DATA18__LCD_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
288 MX7D_PAD_LCD_DATA19__LCD_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
289 MX7D_PAD_LCD_DATA20__LCD_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
290 MX7D_PAD_LCD_DATA21__LCD_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
291 MX7D_PAD_LCD_DATA22__LCD_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
292 MX7D_PAD_LCD_DATA23__LCD_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL),
294 MX7D_PAD_LCD_RESET__GPIO3_IO4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
297 static iomux_v3_cfg_t const pwm_pads[] = {
298 /* Use GPIO for Brightness adjustment, duty cycle = period */
299 MX7D_PAD_GPIO1_IO01__GPIO1_IO1 | MUX_PAD_CTRL(NO_PAD_CTRL),
302 static int setup_lcd(void)
304 imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
306 imx_iomux_v3_setup_multiple_pads(pwm_pads, ARRAY_SIZE(pwm_pads));
309 gpio_direction_output(IMX_GPIO_NR(3, 4) , 0);
311 gpio_direction_output(IMX_GPIO_NR(3, 4) , 1);
313 /* Set Brightness to high */
314 gpio_direction_output(IMX_GPIO_NR(1, 1) , 1);
320 #ifdef CONFIG_FEC_MXC
321 static iomux_v3_cfg_t const fec1_pads[] = {
322 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
323 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
324 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
325 MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
326 MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
327 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
328 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
329 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
330 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
331 MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
332 MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
333 MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
334 MX7D_PAD_GPIO1_IO10__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
335 MX7D_PAD_GPIO1_IO11__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
338 static void setup_iomux_fec(void)
340 imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
344 static void setup_iomux_uart(void)
346 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
349 #ifdef CONFIG_FSL_ESDHC
351 #define USDHC1_CD_GPIO IMX_GPIO_NR(5, 0)
352 #define USDHC1_PWR_GPIO IMX_GPIO_NR(5, 2)
353 #define USDHC3_PWR_GPIO IMX_GPIO_NR(6, 11)
355 static struct fsl_esdhc_cfg usdhc_cfg[3] = {
356 {USDHC1_BASE_ADDR, 0, 4},
360 int board_mmc_get_env_dev(int devno)
368 static int mmc_map_to_kernel_blk(int dev_no)
376 int board_mmc_getcd(struct mmc *mmc)
378 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
381 switch (cfg->esdhc_base) {
382 case USDHC1_BASE_ADDR:
383 ret = !gpio_get_value(USDHC1_CD_GPIO);
385 case USDHC3_BASE_ADDR:
386 ret = 1; /* Assume uSDHC3 emmc is always present */
393 int board_mmc_init(bd_t *bis)
397 * According to the board_mmc_init() the following map is done:
398 * (U-Boot device node) (Physical Port)
402 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
405 imx_iomux_v3_setup_multiple_pads(
406 usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
407 gpio_request(USDHC1_CD_GPIO, "usdhc1_cd");
408 gpio_direction_input(USDHC1_CD_GPIO);
409 gpio_request(USDHC1_PWR_GPIO, "usdhc1_pwr");
410 gpio_direction_output(USDHC1_PWR_GPIO, 0);
412 gpio_direction_output(USDHC1_PWR_GPIO, 1);
413 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
416 imx_iomux_v3_setup_multiple_pads(
417 usdhc3_emmc_pads, ARRAY_SIZE(usdhc3_emmc_pads));
418 gpio_request(USDHC3_PWR_GPIO, "usdhc3_pwr");
419 gpio_direction_output(USDHC3_PWR_GPIO, 0);
421 gpio_direction_output(USDHC3_PWR_GPIO, 1);
422 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
425 printf("Warning: you configured more USDHC controllers"
426 "(%d) than supported by the board\n", i + 1);
430 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
438 static int check_mmc_autodetect(void)
440 char *autodetect_str = getenv("mmcautodetect");
442 if ((autodetect_str != NULL) &&
443 (strcmp(autodetect_str, "yes") == 0)) {
450 static void mmc_late_init(void)
454 u32 dev_no = mmc_get_env_dev();
456 if (!check_mmc_autodetect())
459 setenv_ulong("mmcdev", dev_no);
462 sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw",
463 mmc_map_to_kernel_blk(dev_no));
464 setenv("mmcroot", mmcblk);
466 sprintf(cmd, "mmc dev %d", dev_no);
472 #ifdef CONFIG_FEC_MXC
473 int board_eth_init(bd_t *bis)
479 ret = fecmxc_initialize_multi(bis, 0,
480 CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
482 printf("FEC1 MXC: %s:failed\n", __func__);
487 static int setup_fec(void)
489 struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
490 = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
492 /* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/
493 clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
494 (IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK |
495 IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0);
497 return set_clk_enet(ENET_125MHz);
501 int board_phy_config(struct phy_device *phydev)
503 /* enable rgmii rxc skew and phy mode select to RGMII copper */
504 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x21);
505 phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x7ea8);
506 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x2f);
507 phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x71b7);
509 if (phydev->drv->config)
510 phydev->drv->config(phydev);
515 #ifdef CONFIG_FSL_QSPI
516 static iomux_v3_cfg_t const quadspi_pads[] = {
517 MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
518 MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
519 MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
520 MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
521 MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL),
522 MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL),
525 int board_qspi_init(void)
528 imx_iomux_v3_setup_multiple_pads(quadspi_pads,
529 ARRAY_SIZE(quadspi_pads));
538 int board_early_init_f(void)
542 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
543 imx_iomux_v3_setup_multiple_pads(usb_otg1_pads,
544 ARRAY_SIZE(usb_otg1_pads));
545 imx_iomux_v3_setup_multiple_pads(usb_otg2_pads,
546 ARRAY_SIZE(usb_otg2_pads));
553 /* address of boot parameters */
554 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
556 imx_iomux_v3_setup_multiple_pads(iox_pads, ARRAY_SIZE(iox_pads));
560 #ifdef CONFIG_FEC_MXC
564 #ifdef CONFIG_NAND_MXS
568 #ifdef CONFIG_VIDEO_MXS
572 #ifdef CONFIG_FSL_QSPI
576 #ifdef CONFIG_MXC_SPI
585 int power_init_board(void)
589 unsigned int reg, rev_id;
591 ret = power_pfuze3000_init(I2C_PMIC);
595 p = pmic_get("PFUZE3000");
600 pmic_reg_read(p, PFUZE3000_DEVICEID, ®);
601 pmic_reg_read(p, PFUZE3000_REVID, &rev_id);
602 printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
604 /* disable Low Power Mode during standby mode */
605 pmic_reg_write(p, PFUZE3000_LDOGCTL, 0x1);
611 int board_late_init(void)
613 struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
615 #ifdef CONFIG_ENV_IS_IN_MMC
619 imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
621 set_wdog_reset(wdog);
624 * Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4),
625 * since we use PMIC_PWRON to reset the board.
627 clrsetbits_le16(&wdog->wcr, 0, 0x10);
636 if (IS_ENABLED(CONFIG_ARMV7_BOOT_SEC_DEFAULT))
641 printf("Board: i.MX7D SABRESD in %s mode\n", mode);
646 #ifdef CONFIG_USB_EHCI_MX7
647 int board_usb_phy_mode(int port)
650 return USB_INIT_DEVICE;
652 return USB_INIT_HOST;