2 * Copyright (C) 2015 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
7 #include <asm/arch/clock.h>
8 #include <asm/arch/imx-regs.h>
9 #include <asm/arch/mx7-pins.h>
10 #include <asm/arch/sys_proto.h>
12 #include <asm/imx-common/iomux-v3.h>
13 #include <asm/imx-common/boot_mode.h>
15 #include <linux/sizes.h>
17 #include <fsl_esdhc.h>
21 #include <power/pmic.h>
22 #include <power/pfuze3000_pmic.h>
23 #include "../common/pfuze.h"
25 #include <asm/imx-common/mxc_i2c.h>
26 #include <asm/arch/crm_regs.h>
28 DECLARE_GLOBAL_DATA_PTR;
30 #define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
31 PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
33 #define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
34 PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
36 #define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
37 #define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM)
39 #define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
41 #define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
42 PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM)
44 #ifdef CONFIG_SYS_I2C_MXC
45 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
47 struct i2c_pads_info i2c_pad_info1 = {
49 .i2c_mode = MX7D_PAD_I2C1_SCL__I2C1_SCL | PC,
50 .gpio_mode = MX7D_PAD_I2C1_SCL__GPIO4_IO8 | PC,
51 .gp = IMX_GPIO_NR(4, 8),
54 .i2c_mode = MX7D_PAD_I2C1_SDA__I2C1_SDA | PC,
55 .gpio_mode = MX7D_PAD_I2C1_SDA__GPIO4_IO9 | PC,
56 .gp = IMX_GPIO_NR(4, 9),
63 gd->ram_size = PHYS_SDRAM_SIZE;
68 static iomux_v3_cfg_t const wdog_pads[] = {
69 MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),
72 static iomux_v3_cfg_t const uart1_pads[] = {
73 MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
74 MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
77 static iomux_v3_cfg_t const usdhc1_pads[] = {
78 MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
79 MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
80 MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
81 MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
82 MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
83 MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
85 MX7D_PAD_SD1_CD_B__GPIO5_IO0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
86 MX7D_PAD_SD1_RESET_B__GPIO5_IO2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
89 static iomux_v3_cfg_t const usdhc3_emmc_pads[] = {
90 MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
91 MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
92 MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
93 MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
94 MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
95 MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
96 MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
97 MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
98 MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
99 MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
100 MX7D_PAD_SD3_STROBE__SD3_STROBE | MUX_PAD_CTRL(USDHC_PAD_CTRL),
102 MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
105 #define IOX_SDI IMX_GPIO_NR(1, 9)
106 #define IOX_STCP IMX_GPIO_NR(1, 12)
107 #define IOX_SHCP IMX_GPIO_NR(1, 13)
109 static iomux_v3_cfg_t const iox_pads[] = {
111 MX7D_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL),
113 MX7D_PAD_GPIO1_IO12__GPIO1_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
115 MX7D_PAD_GPIO1_IO13__GPIO1_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL),
123 * SENSOR_RST_B --> Q4
150 static enum qn_level seq[3][2] = {
151 {0, 1}, {1, 1}, {0, 0}
154 static enum qn_func qn_output[8] = {
155 qn_disable, qn_reset, qn_reset, qn_reset, qn_reset, qn_reset, qn_enable,
159 void iox74lv_init(void)
163 for (i = 7; i >= 0; i--) {
164 gpio_direction_output(IOX_SHCP, 0);
165 gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]);
167 gpio_direction_output(IOX_SHCP, 1);
171 gpio_direction_output(IOX_STCP, 0);
174 * shift register will be output to pins
176 gpio_direction_output(IOX_STCP, 1);
178 for (i = 7; i >= 0; i--) {
179 gpio_direction_output(IOX_SHCP, 0);
180 gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]);
182 gpio_direction_output(IOX_SHCP, 1);
185 gpio_direction_output(IOX_STCP, 0);
188 * shift register will be output to pins
190 gpio_direction_output(IOX_STCP, 1);
193 void iox74lv_set(int index)
196 for (i = 7; i >= 0; i--) {
197 gpio_direction_output(IOX_SHCP, 0);
200 gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]);
202 gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]);
204 gpio_direction_output(IOX_SHCP, 1);
208 gpio_direction_output(IOX_STCP, 0);
211 * shift register will be output to pins
213 gpio_direction_output(IOX_STCP, 1);
215 for (i = 7; i >= 0; i--) {
216 gpio_direction_output(IOX_SHCP, 0);
217 gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]);
219 gpio_direction_output(IOX_SHCP, 1);
223 gpio_direction_output(IOX_STCP, 0);
226 * shift register will be output to pins
228 gpio_direction_output(IOX_STCP, 1);
231 #ifdef CONFIG_FEC_MXC
232 static iomux_v3_cfg_t const fec1_pads[] = {
233 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
234 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
235 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
236 MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
237 MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
238 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
239 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
240 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
241 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
242 MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
243 MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
244 MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
245 MX7D_PAD_GPIO1_IO10__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
246 MX7D_PAD_GPIO1_IO11__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
249 static void setup_iomux_fec(void)
251 imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
255 static void setup_iomux_uart(void)
257 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
260 #ifdef CONFIG_FSL_ESDHC
262 #define USDHC1_CD_GPIO IMX_GPIO_NR(5, 0)
263 #define USDHC1_PWR_GPIO IMX_GPIO_NR(5, 2)
264 #define USDHC3_PWR_GPIO IMX_GPIO_NR(6, 11)
266 static struct fsl_esdhc_cfg usdhc_cfg[3] = {
267 {USDHC1_BASE_ADDR, 0, 4},
271 static int mmc_get_env_devno(void)
273 struct bootrom_sw_info **p =
274 (struct bootrom_sw_info **)ROM_SW_INFO_ADDR;
276 u8 boot_type = (*p)->boot_dev_type;
277 u8 dev_no = (*p)->boot_dev_instance;
279 /* If not boot from sd/mmc, use default value */
280 if ((boot_type != BOOT_TYPE_SD) && (boot_type != BOOT_TYPE_MMC))
281 return CONFIG_SYS_MMC_ENV_DEV;
289 static int mmc_map_to_kernel_blk(int dev_no)
297 int board_mmc_getcd(struct mmc *mmc)
299 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
302 switch (cfg->esdhc_base) {
303 case USDHC1_BASE_ADDR:
304 ret = !gpio_get_value(USDHC1_CD_GPIO);
306 case USDHC3_BASE_ADDR:
307 ret = 1; /* Assume uSDHC3 emmc is always present */
314 int board_mmc_init(bd_t *bis)
318 * According to the board_mmc_init() the following map is done:
319 * (U-boot device node) (Physical Port)
323 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
326 imx_iomux_v3_setup_multiple_pads(
327 usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
328 gpio_request(USDHC1_CD_GPIO, "usdhc1_cd");
329 gpio_direction_input(USDHC1_CD_GPIO);
330 gpio_request(USDHC1_PWR_GPIO, "usdhc1_pwr");
331 gpio_direction_output(USDHC1_PWR_GPIO, 0);
333 gpio_direction_output(USDHC1_PWR_GPIO, 1);
334 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
337 imx_iomux_v3_setup_multiple_pads(
338 usdhc3_emmc_pads, ARRAY_SIZE(usdhc3_emmc_pads));
339 gpio_request(USDHC3_PWR_GPIO, "usdhc3_pwr");
340 gpio_direction_output(USDHC3_PWR_GPIO, 0);
342 gpio_direction_output(USDHC3_PWR_GPIO, 1);
343 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
346 printf("Warning: you configured more USDHC controllers"
347 "(%d) than supported by the board\n", i + 1);
351 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
359 static int check_mmc_autodetect(void)
361 char *autodetect_str = getenv("mmcautodetect");
363 if ((autodetect_str != NULL) &&
364 (strcmp(autodetect_str, "yes") == 0)) {
371 static void mmc_late_init(void)
375 u32 dev_no = mmc_get_env_devno();
377 if (!check_mmc_autodetect())
380 setenv_ulong("mmcdev", dev_no);
383 sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw",
384 mmc_map_to_kernel_blk(dev_no));
385 setenv("mmcroot", mmcblk);
387 sprintf(cmd, "mmc dev %d", dev_no);
393 #ifdef CONFIG_FEC_MXC
394 int board_eth_init(bd_t *bis)
400 ret = fecmxc_initialize_multi(bis, 0,
401 CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
403 printf("FEC1 MXC: %s:failed\n", __func__);
408 static int setup_fec(void)
410 struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
411 = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
413 /* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/
414 clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
415 (IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK |
416 IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0);
418 return set_clk_enet(ENET_125MHz);
422 int board_phy_config(struct phy_device *phydev)
424 /* enable rgmii rxc skew and phy mode select to RGMII copper */
425 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x21);
426 phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x7ea8);
427 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x2f);
428 phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x71b7);
430 if (phydev->drv->config)
431 phydev->drv->config(phydev);
436 int board_early_init_f(void)
440 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
447 /* address of boot parameters */
448 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
450 imx_iomux_v3_setup_multiple_pads(iox_pads, ARRAY_SIZE(iox_pads));
454 #ifdef CONFIG_FEC_MXC
461 #ifdef CONFIG_CMD_BMODE
462 static const struct boot_mode board_boot_modes[] = {
463 /* 4 bit bus width */
464 {"sd1", MAKE_CFGVAL(0x10, 0x10, 0x00, 0x00)},
465 {"emmc", MAKE_CFGVAL(0x10, 0x2a, 0x00, 0x00)},
472 int power_init_board(void)
476 unsigned int reg, rev_id;
478 ret = power_pfuze3000_init(I2C_PMIC);
482 p = pmic_get("PFUZE3000");
487 pmic_reg_read(p, PFUZE3000_DEVICEID, ®);
488 pmic_reg_read(p, PFUZE3000_REVID, &rev_id);
489 printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
491 /* disable Low Power Mode during standby mode */
492 pmic_reg_read(p, PFUZE3000_LDOGCTL, ®);
494 pmic_reg_write(p, PFUZE3000_LDOGCTL, reg);
500 int board_late_init(void)
502 #ifdef CONFIG_CMD_BMODE
503 add_board_boot_modes(board_boot_modes);
506 #ifdef CONFIG_ENV_IS_IN_MMC
510 imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
512 set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR);
517 u32 get_board_rev(void)
519 return get_cpu_rev();
524 puts("Board: i.MX7D SABRESD\n");
529 #ifdef CONFIG_USB_EHCI_MX7
530 iomux_v3_cfg_t const usb_otg1_pads[] = {
531 MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
534 iomux_v3_cfg_t const usb_otg2_pads[] = {
535 MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
538 int board_ehci_hcd_init(int port)
542 imx_iomux_v3_setup_multiple_pads(usb_otg1_pads,
543 ARRAY_SIZE(usb_otg1_pads));
546 imx_iomux_v3_setup_multiple_pads(usb_otg2_pads,
547 ARRAY_SIZE(usb_otg2_pads));
550 printf("MXC USB port %d not yet supported\n", port);