1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2016 Freescale Semiconductor, Inc.
7 #include <asm/arch/clock.h>
8 #include <asm/arch/iomux.h>
9 #include <asm/arch/imx-regs.h>
10 #include <asm/arch/crm_regs.h>
11 #include <asm/arch/mx6-pins.h>
12 #include <asm/arch/sys_proto.h>
14 #include <asm/mach-imx/iomux-v3.h>
15 #include <asm/mach-imx/boot_mode.h>
19 #include <fsl_esdhc_imx.h>
20 #include <linux/sizes.h>
24 DECLARE_GLOBAL_DATA_PTR;
26 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
27 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
28 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
32 gd->ram_size = imx_ddr_size();
37 static iomux_v3_cfg_t const uart1_pads[] = {
38 MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
39 MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
42 static void setup_iomux_uart(void)
44 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
47 int board_mmc_get_env_dev(int devno)
52 int mmc_map_to_kernel_blk(int devno)
57 int board_early_init_f(void)
65 static int setup_fec(int fec_id)
67 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
72 * Use 50MHz anatop loopback REF_CLK1 for ENET1,
73 * clear gpr1[13], set gpr1[17].
75 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
76 IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
79 * Use 50MHz anatop loopback REF_CLK2 for ENET2,
80 * clear gpr1[14], set gpr1[18].
82 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
83 IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
86 ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ);
95 int board_phy_config(struct phy_device *phydev)
97 phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
99 if (phydev->drv->config)
100 phydev->drv->config(phydev);
108 /* Address of boot parameters */
109 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
111 #ifdef CONFIG_FEC_MXC
112 setup_fec(CONFIG_FEC_ENET_DEV);
118 #ifdef CONFIG_CMD_BMODE
119 static const struct boot_mode board_boot_modes[] = {
120 /* 4 bit bus width */
121 {"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)},
122 {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
123 {"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
128 int board_late_init(void)
130 #ifdef CONFIG_CMD_BMODE
131 add_board_boot_modes(board_boot_modes);
134 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
135 if (is_cpu_type(MXC_CPU_MX6ULZ))
136 env_set("board_name", "ULZ-EVK");
138 env_set("board_name", "EVK");
139 env_set("board_rev", "14X14");
147 if (is_cpu_type(MXC_CPU_MX6ULZ))
148 puts("Board: MX6ULZ 14x14 EVK\n");
150 puts("Board: MX6ULL 14x14 EVK\n");