board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c

   1 /*
   2  * Copyright (C) 2015 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <asm/arch/clock.h>
   8 #include <asm/arch/iomux.h>
   9 #include <asm/arch/imx-regs.h>
  10 #include <asm/arch/crm_regs.h>
  11 #include <asm/arch/mx6ul_pins.h>
  12 #include <asm/arch/mx6-pins.h>
  13 #include <asm/arch/sys_proto.h>
  14 #include <asm/gpio.h>
  15 #include <asm/imx-common/iomux-v3.h>
  16 #include <asm/imx-common/boot_mode.h>
  17 #include <asm/imx-common/mxc_i2c.h>
  18 #include <asm/io.h>
  19 #include <common.h>
  20 #include <fsl_esdhc.h>
  21 #include <i2c.h>
  22 #include <miiphy.h>
  23 #include <linux/sizes.h>
  24 #include <mmc.h>
  25 #include <netdev.h>
  26 #include <power/pmic.h>
  27 #include <power/pfuze3000_pmic.h>
  28 #include "../common/pfuze.h"
  29 #include <usb.h>
  30 #include <usb/ehci-fsl.h>
  31
  32 DECLARE_GLOBAL_DATA_PTR;
  33
  34 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
  35         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  36         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  37
  38 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |             \
  39         PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |               \
  40         PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  41
  42 #define USDHC_DAT3_CD_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |     \
  43         PAD_CTL_PUS_100K_DOWN  | PAD_CTL_SPEED_LOW |            \
  44         PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  45
  46 #define I2C_PAD_CTRL    (PAD_CTL_PKE | PAD_CTL_PUE |            \
  47         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  48         PAD_CTL_DSE_40ohm | PAD_CTL_HYS |                       \
  49         PAD_CTL_ODE)
  50
  51 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
  52         PAD_CTL_SPEED_HIGH   |                                  \
  53         PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST)
  54
  55 #define MDIO_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
  56         PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST | PAD_CTL_ODE)
  57
  58 #define ENET_CLK_PAD_CTRL  (PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST)
  59
  60 #define ENET_RX_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |          \
  61         PAD_CTL_SPEED_HIGH   | PAD_CTL_SRE_FAST)
  62
  63 #define IOX_SDI IMX_GPIO_NR(5, 10)
  64 #define IOX_STCP IMX_GPIO_NR(5, 7)
  65 #define IOX_SHCP IMX_GPIO_NR(5, 11)
  66 #define IOX_OE IMX_GPIO_NR(5, 18)
  67
  68 static iomux_v3_cfg_t const iox_pads[] = {
  69         /* IOX_SDI */
  70         MX6_PAD_BOOT_MODE0__GPIO5_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
  71         /* IOX_SHCP */
  72         MX6_PAD_BOOT_MODE1__GPIO5_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
  73         /* IOX_STCP */
  74         MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
  75         /* IOX_nOE */
  76         MX6_PAD_SNVS_TAMPER8__GPIO5_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
  77 };
  78
  79 /*
  80  * HDMI_nRST --> Q0
  81  * ENET1_nRST --> Q1
  82  * ENET2_nRST --> Q2
  83  * CAN1_2_STBY --> Q3
  84  * BT_nPWD --> Q4
  85  * CSI_RST --> Q5
  86  * CSI_PWDN --> Q6
  87  * LCD_nPWREN --> Q7
  88  */
  89 enum qn {
  90         HDMI_NRST,
  91         ENET1_NRST,
  92         ENET2_NRST,
  93         CAN1_2_STBY,
  94         BT_NPWD,
  95         CSI_RST,
  96         CSI_PWDN,
  97         LCD_NPWREN,
  98 };
  99
 100 enum qn_func {
 101         qn_reset,
 102         qn_enable,
 103         qn_disable,
 104 };
 105
 106 enum qn_level {
 107         qn_low = 0,
 108         qn_high = 1,
 109 };
 110
 111 static enum qn_level seq[3][2] = {
 112         {0, 1}, {1, 1}, {0, 0}
 113 };
 114
 115 static enum qn_func qn_output[8] = {
 116         qn_reset, qn_reset, qn_reset, qn_enable, qn_disable, qn_reset,
 117         qn_disable, qn_enable
 118 };
 119
 120 static void iox74lv_init(void)
 121 {
 122         int i;
 123
 124         gpio_direction_output(IOX_OE, 0);
 125
 126         for (i = 7; i >= 0; i--) {
 127                 gpio_direction_output(IOX_SHCP, 0);
 128                 gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]);
 129                 udelay(500);
 130                 gpio_direction_output(IOX_SHCP, 1);
 131                 udelay(500);
 132         }
 133
 134         gpio_direction_output(IOX_STCP, 0);
 135         udelay(500);
 136         /*
 137          * shift register will be output to pins
 138          */
 139         gpio_direction_output(IOX_STCP, 1);
 140
 141         for (i = 7; i >= 0; i--) {
 142                 gpio_direction_output(IOX_SHCP, 0);
 143                 gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]);
 144                 udelay(500);
 145                 gpio_direction_output(IOX_SHCP, 1);
 146                 udelay(500);
 147         }
 148         gpio_direction_output(IOX_STCP, 0);
 149         udelay(500);
 150         /*
 151          * shift register will be output to pins
 152          */
 153         gpio_direction_output(IOX_STCP, 1);
 154
 155         gpio_direction_output(IOX_OE, 1);
 156 };
 157
 158 void iox74lv_set(int index)
 159 {
 160         int i;
 161
 162         gpio_direction_output(IOX_OE, 0);
 163
 164         for (i = 7; i >= 0; i--) {
 165                 gpio_direction_output(IOX_SHCP, 0);
 166
 167                 if (i == index)
 168                         gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]);
 169                 else
 170                         gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]);
 171                 udelay(500);
 172                 gpio_direction_output(IOX_SHCP, 1);
 173                 udelay(500);
 174         }
 175
 176         gpio_direction_output(IOX_STCP, 0);
 177         udelay(500);
 178         /*
 179          * shift register will be output to pins
 180          */
 181         gpio_direction_output(IOX_STCP, 1);
 182
 183         for (i = 7; i >= 0; i--) {
 184                 gpio_direction_output(IOX_SHCP, 0);
 185                 gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]);
 186                 udelay(500);
 187                 gpio_direction_output(IOX_SHCP, 1);
 188                 udelay(500);
 189         }
 190
 191         gpio_direction_output(IOX_STCP, 0);
 192         udelay(500);
 193         /*
 194          * shift register will be output to pins
 195          */
 196         gpio_direction_output(IOX_STCP, 1);
 197
 198         gpio_direction_output(IOX_OE, 1);
 199 };
 200
 201 #ifdef CONFIG_SYS_I2C_MXC
 202 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
 203 /* I2C1 for PMIC and EEPROM */
 204 struct i2c_pads_info i2c_pad_info1 = {
 205         .scl = {
 206                 .i2c_mode =  MX6_PAD_UART4_TX_DATA__I2C1_SCL | PC,
 207                 .gpio_mode = MX6_PAD_UART4_TX_DATA__GPIO1_IO28 | PC,
 208                 .gp = IMX_GPIO_NR(1, 28),
 209         },
 210         .sda = {
 211                 .i2c_mode = MX6_PAD_UART4_RX_DATA__I2C1_SDA | PC,
 212                 .gpio_mode = MX6_PAD_UART4_RX_DATA__GPIO1_IO29 | PC,
 213                 .gp = IMX_GPIO_NR(1, 29),
 214         },
 215 };
 216
 217 #ifdef CONFIG_POWER
 218 #define I2C_PMIC       0
 219 int power_init_board(void)
 220 {
 221         if (is_mx6ul_9x9_evk()) {
 222                 struct pmic *pfuze;
 223                 int ret;
 224                 unsigned int reg, rev_id;
 225
 226                 ret = power_pfuze3000_init(I2C_PMIC);
 227                 if (ret)
 228                         return ret;
 229
 230                 pfuze = pmic_get("PFUZE3000");
 231                 ret = pmic_probe(pfuze);
 232                 if (ret)
 233                         return ret;
 234
 235                 pmic_reg_read(pfuze, PFUZE3000_DEVICEID, &reg);
 236                 pmic_reg_read(pfuze, PFUZE3000_REVID, &rev_id);
 237                 printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n",
 238                        reg, rev_id);
 239
 240                 /* disable Low Power Mode during standby mode */
 241                 pmic_reg_read(pfuze, PFUZE3000_LDOGCTL, &reg);
 242                 reg |= 0x1;
 243                 pmic_reg_write(pfuze, PFUZE3000_LDOGCTL, reg);
 244
 245                 /* SW1B step ramp up time from 2us to 4us/25mV */
 246                 reg = 0x40;
 247                 pmic_reg_write(pfuze, PFUZE3000_SW1BCONF, reg);
 248
 249                 /* SW1B mode to APS/PFM */
 250                 reg = 0xc;
 251                 pmic_reg_write(pfuze, PFUZE3000_SW1BMODE, reg);
 252
 253                 /* SW1B standby voltage set to 0.975V */
 254                 reg = 0xb;
 255                 pmic_reg_write(pfuze, PFUZE3000_SW1BSTBY, reg);
 256         }
 257
 258         return 0;
 259 }
 260 #endif
 261 #endif
 262
 263 int dram_init(void)
 264 {
 265         gd->ram_size = imx_ddr_size();
 266
 267         return 0;
 268 }
 269
 270 static iomux_v3_cfg_t const uart1_pads[] = {
 271         MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
 272         MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
 273 };
 274
 275 static iomux_v3_cfg_t const usdhc1_pads[] = {
 276         MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 277         MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 278         MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 279         MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 280         MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 281         MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 282
 283         /* VSELECT */
 284         MX6_PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 285         /* CD */
 286         MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
 287         /* RST_B */
 288         MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
 289 };
 290
 291 /*
 292  * mx6ul_14x14_evk board default supports sd card. If want to use
 293  * EMMC, need to do board rework for sd2.
 294  * Introduce CONFIG_MX6UL_14X14_EVK_EMMC_REWORK, if sd2 reworked to support
 295  * emmc, need to define this macro.
 296  */
 297 #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
 298 static iomux_v3_cfg_t const usdhc2_emmc_pads[] = {
 299         MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 300         MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 301         MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 302         MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 303         MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 304         MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 305         MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 306         MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 307         MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 308         MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 309
 310         /*
 311          * RST_B
 312          */
 313         MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
 314 };
 315 #else
 316 static iomux_v3_cfg_t const usdhc2_pads[] = {
 317         MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 318         MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 319         MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 320         MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 321         MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 322         MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 323 };
 324
 325 static iomux_v3_cfg_t const usdhc2_cd_pads[] = {
 326         /*
 327          * The evk board uses DAT3 to detect CD card plugin,
 328          * in u-boot we mux the pin to GPIO when doing board_mmc_getcd.
 329          */
 330         MX6_PAD_NAND_DATA03__GPIO4_IO05 | MUX_PAD_CTRL(USDHC_DAT3_CD_PAD_CTRL),
 331 };
 332
 333 static iomux_v3_cfg_t const usdhc2_dat3_pads[] = {
 334         MX6_PAD_NAND_DATA03__USDHC2_DATA3 |
 335         MUX_PAD_CTRL(USDHC_DAT3_CD_PAD_CTRL),
 336 };
 337 #endif
 338
 339 static void setup_iomux_uart(void)
 340 {
 341         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 342 }
 343
 344 #ifdef CONFIG_FSL_QSPI
 345
 346 #define QSPI_PAD_CTRL1  \
 347         (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \
 348          PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_60ohm)
 349
 350 static iomux_v3_cfg_t const quadspi_pads[] = {
 351         MX6_PAD_NAND_WP_B__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
 352         MX6_PAD_NAND_READY_B__QSPI_A_DATA00 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
 353         MX6_PAD_NAND_CE0_B__QSPI_A_DATA01 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
 354         MX6_PAD_NAND_CE1_B__QSPI_A_DATA02 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
 355         MX6_PAD_NAND_CLE__QSPI_A_DATA03 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
 356         MX6_PAD_NAND_DQS__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
 357 };
 358
 359 int board_qspi_init(void)
 360 {
 361         /* Set the iomux */
 362         imx_iomux_v3_setup_multiple_pads(quadspi_pads,
 363                                          ARRAY_SIZE(quadspi_pads));
 364         /* Set the clock */
 365         enable_qspi_clk(0);
 366
 367         return 0;
 368 }
 369 #endif
 370
 371 #ifdef CONFIG_FSL_ESDHC
 372 static struct fsl_esdhc_cfg usdhc_cfg[2] = {
 373         {USDHC1_BASE_ADDR, 0, 4},
 374 #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
 375         {USDHC2_BASE_ADDR, 0, 8},
 376 #else
 377         {USDHC2_BASE_ADDR, 0, 4},
 378 #endif
 379 };
 380
 381 #define USDHC1_CD_GPIO  IMX_GPIO_NR(1, 19)
 382 #define USDHC1_PWR_GPIO IMX_GPIO_NR(1, 9)
 383 #define USDHC2_CD_GPIO  IMX_GPIO_NR(4, 5)
 384 #define USDHC2_PWR_GPIO IMX_GPIO_NR(4, 10)
 385
 386 int board_mmc_getcd(struct mmc *mmc)
 387 {
 388         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 389         int ret = 0;
 390
 391         switch (cfg->esdhc_base) {
 392         case USDHC1_BASE_ADDR:
 393                 ret = !gpio_get_value(USDHC1_CD_GPIO);
 394                 break;
 395         case USDHC2_BASE_ADDR:
 396 #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
 397                 ret = 1;
 398 #else
 399                 imx_iomux_v3_setup_multiple_pads(usdhc2_cd_pads,
 400                                                  ARRAY_SIZE(usdhc2_cd_pads));
 401                 gpio_direction_input(USDHC2_CD_GPIO);
 402
 403                 /*
 404                  * Since it is the DAT3 pin, this pin is pulled to
 405                  * low voltage if no card
 406                  */
 407                 ret = gpio_get_value(USDHC2_CD_GPIO);
 408
 409                 imx_iomux_v3_setup_multiple_pads(usdhc2_dat3_pads,
 410                                                  ARRAY_SIZE(usdhc2_dat3_pads));
 411 #endif
 412                 break;
 413         }
 414
 415         return ret;
 416 }
 417
 418 int board_mmc_init(bd_t *bis)
 419 {
 420 #ifdef CONFIG_SPL_BUILD
 421 #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
 422         imx_iomux_v3_setup_multiple_pads(usdhc2_emmc_pads,
 423                                          ARRAY_SIZE(usdhc2_emmc_pads));
 424 #else
 425         imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
 426 #endif
 427         gpio_direction_output(USDHC2_PWR_GPIO, 0);
 428         udelay(500);
 429         gpio_direction_output(USDHC2_PWR_GPIO, 1);
 430         usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 431         return fsl_esdhc_initialize(bis, &usdhc_cfg[1]);
 432 #else
 433         int i, ret;
 434
 435         /*
 436          * According to the board_mmc_init() the following map is done:
 437          * (U-boot device node)    (Physical Port)
 438          * mmc0                    USDHC1
 439          * mmc1                    USDHC2
 440          */
 441         for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
 442                 switch (i) {
 443                 case 0:
 444                         imx_iomux_v3_setup_multiple_pads(
 445                                 usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
 446                         gpio_direction_input(USDHC1_CD_GPIO);
 447                         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 448
 449                         gpio_direction_output(USDHC1_PWR_GPIO, 0);
 450                         udelay(500);
 451                         gpio_direction_output(USDHC1_PWR_GPIO, 1);
 452                         break;
 453                 case 1:
 454 #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
 455                         imx_iomux_v3_setup_multiple_pads(
 456                                 usdhc2_emmc_pads, ARRAY_SIZE(usdhc2_emmc_pads));
 457 #else
 458                         imx_iomux_v3_setup_multiple_pads(
 459                                 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
 460 #endif
 461                         gpio_direction_output(USDHC2_PWR_GPIO, 0);
 462                         udelay(500);
 463                         gpio_direction_output(USDHC2_PWR_GPIO, 1);
 464                         usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 465                         break;
 466                 default:
 467                         printf("Warning: you configured more USDHC controllers (%d) than supported by the board\n", i + 1);
 468                         return -EINVAL;
 469                         }
 470
 471                         ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 472                         if (ret) {
 473                                 printf("Warning: failed to initialize mmc dev %d\n", i);
 474                                 return ret;
 475                         }
 476         }
 477 #endif
 478         return 0;
 479 }
 480 #endif
 481
 482 #ifdef CONFIG_USB_EHCI_MX6
 483 #define USB_OTHERREGS_OFFSET    0x800
 484 #define UCTRL_PWR_POL           (1 << 9)
 485
 486 static iomux_v3_cfg_t const usb_otg_pads[] = {
 487         MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
 488 };
 489
 490 /* At default the 3v3 enables the MIC2026 for VBUS power */
 491 static void setup_usb(void)
 492 {
 493         imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
 494                                          ARRAY_SIZE(usb_otg_pads));
 495 }
 496
 497 int board_usb_phy_mode(int port)
 498 {
 499         if (port == 1)
 500                 return USB_INIT_HOST;
 501         else
 502                 return usb_phy_mode(port);
 503 }
 504
 505 int board_ehci_hcd_init(int port)
 506 {
 507         u32 *usbnc_usb_ctrl;
 508
 509         if (port > 1)
 510                 return -EINVAL;
 511
 512         usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
 513                                  port * 4);
 514
 515         /* Set Power polarity */
 516         setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
 517
 518         return 0;
 519 }
 520 #endif
 521
 522 #ifdef CONFIG_FEC_MXC
 523 /*
 524  * pin conflicts for fec1 and fec2, GPIO1_IO06 and GPIO1_IO07 can only
 525  * be used for ENET1 or ENET2, cannot be used for both.
 526  */
 527 static iomux_v3_cfg_t const fec1_pads[] = {
 528         MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
 529         MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
 530         MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 531         MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 532         MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
 533         MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
 534         MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 535         MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 536         MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
 537         MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
 538 };
 539
 540 static iomux_v3_cfg_t const fec2_pads[] = {
 541         MX6_PAD_GPIO1_IO06__ENET2_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
 542         MX6_PAD_GPIO1_IO07__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
 543
 544         MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 545         MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 546         MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
 547         MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
 548
 549         MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 550         MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 551         MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
 552         MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
 553 };
 554
 555 static void setup_iomux_fec(int fec_id)
 556 {
 557         if (fec_id == 0)
 558                 imx_iomux_v3_setup_multiple_pads(fec1_pads,
 559                                                  ARRAY_SIZE(fec1_pads));
 560         else
 561                 imx_iomux_v3_setup_multiple_pads(fec2_pads,
 562                                                  ARRAY_SIZE(fec2_pads));
 563 }
 564
 565 int board_eth_init(bd_t *bis)
 566 {
 567         setup_iomux_fec(CONFIG_FEC_ENET_DEV);
 568
 569         return fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV,
 570                                        CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
 571 }
 572
 573 static int setup_fec(int fec_id)
 574 {
 575         struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 576         int ret;
 577
 578         if (fec_id == 0) {
 579                 /*
 580                  * Use 50M anatop loopback REF_CLK1 for ENET1,
 581                  * clear gpr1[13], set gpr1[17].
 582                  */
 583                 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
 584                                 IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
 585         } else {
 586                 /*
 587                  * Use 50M anatop loopback REF_CLK2 for ENET2,
 588                  * clear gpr1[14], set gpr1[18].
 589                  */
 590                 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
 591                                 IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
 592         }
 593
 594         ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ);
 595         if (ret)
 596                 return ret;
 597
 598         enable_enet_clk(1);
 599
 600         return 0;
 601 }
 602
 603 int board_phy_config(struct phy_device *phydev)
 604 {
 605         phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
 606
 607         if (phydev->drv->config)
 608                 phydev->drv->config(phydev);
 609
 610         return 0;
 611 }
 612 #endif
 613
 614 int board_early_init_f(void)
 615 {
 616         setup_iomux_uart();
 617
 618         return 0;
 619 }
 620
 621 int board_init(void)
 622 {
 623         /* Address of boot parameters */
 624         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 625
 626         imx_iomux_v3_setup_multiple_pads(iox_pads, ARRAY_SIZE(iox_pads));
 627
 628         iox74lv_init();
 629
 630 #ifdef CONFIG_SYS_I2C_MXC
 631         setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 632 #endif
 633
 634 #ifdef  CONFIG_FEC_MXC
 635         setup_fec(CONFIG_FEC_ENET_DEV);
 636 #endif
 637
 638 #ifdef CONFIG_USB_EHCI_MX6
 639         setup_usb();
 640 #endif
 641
 642 #ifdef CONFIG_FSL_QSPI
 643         board_qspi_init();
 644 #endif
 645
 646         return 0;
 647 }
 648
 649 #ifdef CONFIG_CMD_BMODE
 650 static const struct boot_mode board_boot_modes[] = {
 651         /* 4 bit bus width */
 652         {"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)},
 653         {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
 654         {"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
 655         {NULL,   0},
 656 };
 657 #endif
 658
 659 int board_late_init(void)
 660 {
 661 #ifdef CONFIG_CMD_BMODE
 662         add_board_boot_modes(board_boot_modes);
 663 #endif
 664
 665 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 666         setenv("board_name", "EVK");
 667
 668         if (is_mx6ul_9x9_evk())
 669                 setenv("board_rev", "9X9");
 670         else
 671                 setenv("board_rev", "14X14");
 672 #endif
 673
 674         return 0;
 675 }
 676
 677 u32 get_board_rev(void)
 678 {
 679         return get_cpu_rev();
 680 }
 681
 682 int checkboard(void)
 683 {
 684         if (is_mx6ul_9x9_evk())
 685                 puts("Board: MX6UL 9x9 EVK\n");
 686         else
 687                 puts("Board: MX6UL 14x14 EVK\n");
 688
 689         return 0;
 690 }
 691
 692 #ifdef CONFIG_SPL_BUILD
 693 #include <libfdt.h>
 694 #include <spl.h>
 695 #include <asm/arch/mx6-ddr.h>
 696
 697
 698 static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
 699         .grp_addds = 0x00000030,
 700         .grp_ddrmode_ctl = 0x00020000,
 701         .grp_b0ds = 0x00000030,
 702         .grp_ctlds = 0x00000030,
 703         .grp_b1ds = 0x00000030,
 704         .grp_ddrpke = 0x00000000,
 705         .grp_ddrmode = 0x00020000,
 706 #ifdef CONFIG_TARGET_MX6UL_9X9_EVK
 707         .grp_ddr_type = 0x00080000,
 708 #else
 709         .grp_ddr_type = 0x000c0000,
 710 #endif
 711 };
 712
 713 #ifdef CONFIG_TARGET_MX6UL_9X9_EVK
 714 static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
 715         .dram_dqm0 = 0x00000030,
 716         .dram_dqm1 = 0x00000030,
 717         .dram_ras = 0x00000030,
 718         .dram_cas = 0x00000030,
 719         .dram_odt0 = 0x00000000,
 720         .dram_odt1 = 0x00000000,
 721         .dram_sdba2 = 0x00000000,
 722         .dram_sdclk_0 = 0x00000030,
 723         .dram_sdqs0 = 0x00003030,
 724         .dram_sdqs1 = 0x00003030,
 725         .dram_reset = 0x00000030,
 726 };
 727
 728 static struct mx6_mmdc_calibration mx6_mmcd_calib = {
 729         .p0_mpwldectrl0 = 0x00000000,
 730         .p0_mpdgctrl0 = 0x20000000,
 731         .p0_mprddlctl = 0x4040484f,
 732         .p0_mpwrdlctl = 0x40405247,
 733         .mpzqlp2ctl = 0x1b4700c7,
 734 };
 735
 736 static struct mx6_lpddr2_cfg mem_ddr = {
 737         .mem_speed = 800,
 738         .density = 2,
 739         .width = 16,
 740         .banks = 4,
 741         .rowaddr = 14,
 742         .coladdr = 10,
 743         .trcd_lp = 1500,
 744         .trppb_lp = 1500,
 745         .trpab_lp = 2000,
 746         .trasmin = 4250,
 747 };
 748
 749 struct mx6_ddr_sysinfo ddr_sysinfo = {
 750         .dsize = 0,
 751         .cs_density = 18,
 752         .ncs = 1,
 753         .cs1_mirror = 0,
 754         .walat = 0,
 755         .ralat = 5,
 756         .mif3_mode = 3,
 757         .bi_on = 1,
 758         .rtt_wr = 0,        /* LPDDR2 does not need rtt_wr rtt_nom */
 759         .rtt_nom = 0,
 760         .sde_to_rst = 0,    /* LPDDR2 does not need this field */
 761         .rst_to_cke = 0x10, /* JEDEC value for LPDDR2: 200us */
 762         .ddr_type = DDR_TYPE_LPDDR2,
 763 };
 764
 765 #else
 766 static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
 767         .dram_dqm0 = 0x00000030,
 768         .dram_dqm1 = 0x00000030,
 769         .dram_ras = 0x00000030,
 770         .dram_cas = 0x00000030,
 771         .dram_odt0 = 0x00000030,
 772         .dram_odt1 = 0x00000030,
 773         .dram_sdba2 = 0x00000000,
 774         .dram_sdclk_0 = 0x00000008,
 775         .dram_sdqs0 = 0x00000038,
 776         .dram_sdqs1 = 0x00000030,
 777         .dram_reset = 0x00000030,
 778 };
 779
 780 static struct mx6_mmdc_calibration mx6_mmcd_calib = {
 781         .p0_mpwldectrl0 = 0x00070007,
 782         .p0_mpdgctrl0 = 0x41490145,
 783         .p0_mprddlctl = 0x40404546,
 784         .p0_mpwrdlctl = 0x4040524D,
 785 };
 786
 787 struct mx6_ddr_sysinfo ddr_sysinfo = {
 788         .dsize = 0,
 789         .cs_density = 20,
 790         .ncs = 1,
 791         .cs1_mirror = 0,
 792         .rtt_wr = 2,
 793         .rtt_nom = 1,           /* RTT_Nom = RZQ/2 */
 794         .walat = 1,             /* Write additional latency */
 795         .ralat = 5,             /* Read additional latency */
 796         .mif3_mode = 3,         /* Command prediction working mode */
 797         .bi_on = 1,             /* Bank interleaving enabled */
 798         .sde_to_rst = 0x10,     /* 14 cycles, 200us (JEDEC default) */
 799         .rst_to_cke = 0x23,     /* 33 cycles, 500us (JEDEC default) */
 800         .ddr_type = DDR_TYPE_DDR3,
 801 };
 802
 803 static struct mx6_ddr3_cfg mem_ddr = {
 804         .mem_speed = 800,
 805         .density = 4,
 806         .width = 16,
 807         .banks = 8,
 808         .rowaddr = 15,
 809         .coladdr = 10,
 810         .pagesz = 2,
 811         .trcd = 1375,
 812         .trcmin = 4875,
 813         .trasmin = 3500,
 814 };
 815 #endif
 816
 817 static void ccgr_init(void)
 818 {
 819         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 820
 821         writel(0xFFFFFFFF, &ccm->CCGR0);
 822         writel(0xFFFFFFFF, &ccm->CCGR1);
 823         writel(0xFFFFFFFF, &ccm->CCGR2);
 824         writel(0xFFFFFFFF, &ccm->CCGR3);
 825         writel(0xFFFFFFFF, &ccm->CCGR4);
 826         writel(0xFFFFFFFF, &ccm->CCGR5);
 827         writel(0xFFFFFFFF, &ccm->CCGR6);
 828         writel(0xFFFFFFFF, &ccm->CCGR7);
 829 }
 830
 831 static void spl_dram_init(void)
 832 {
 833         mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
 834         mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
 835 }
 836
 837 void board_init_f(ulong dummy)
 838 {
 839         /* setup AIPS and disable watchdog */
 840         arch_cpu_init();
 841
 842         ccgr_init();
 843
 844         /* iomux and setup of i2c */
 845         board_early_init_f();
 846
 847         /* setup GP timer */
 848         timer_init();
 849
 850         /* UART clocks enabled and gd valid - init serial console */
 851         preloader_console_init();
 852
 853         /* DDR initialization */
 854         spl_dram_init();
 855
 856         /* Clear the BSS. */
 857         memset(__bss_start, 0, __bss_end - __bss_start);
 858
 859         /* load/boot image from boot device */
 860         board_init_r(NULL, 0);
 861 }
 862
 863 void reset_cpu(ulong addr)
 864 {
 865 }
 866 #endif