1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015 Freescale Semiconductor, Inc.
6 #include <asm/arch/clock.h>
7 #include <asm/arch/iomux.h>
8 #include <asm/arch/imx-regs.h>
9 #include <asm/arch/crm_regs.h>
10 #include <asm/arch/mx6ul_pins.h>
11 #include <asm/arch/mx6-pins.h>
12 #include <asm/arch/sys_proto.h>
14 #include <asm/mach-imx/iomux-v3.h>
15 #include <asm/mach-imx/boot_mode.h>
16 #include <asm/mach-imx/mxc_i2c.h>
20 #include <fsl_esdhc_imx.h>
23 #include <linux/sizes.h>
26 #include <power/pmic.h>
27 #include <power/pfuze3000_pmic.h>
28 #include "../common/pfuze.h"
30 #include <usb/ehci-ci.h>
32 DECLARE_GLOBAL_DATA_PTR;
34 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
35 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
36 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
38 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
39 PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
40 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
42 #define USDHC_DAT3_CD_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
43 PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_LOW | \
44 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
46 #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
47 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
48 PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
51 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
52 PAD_CTL_SPEED_HIGH | \
53 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
55 #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
56 PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
58 #define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
59 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | PAD_CTL_ODE)
61 #define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
63 #define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
64 PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
65 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
68 int power_init_board(void)
71 int ret, dev_id, rev_id;
74 ret = pmic_get("pfuze3000", &dev);
80 dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID);
81 rev_id = pmic_reg_read(dev, PFUZE3000_REVID);
82 printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
84 /* disable Low Power Mode during standby mode */
85 reg = pmic_reg_read(dev, PFUZE3000_LDOGCTL);
87 pmic_reg_write(dev, PFUZE3000_LDOGCTL, reg);
89 /* SW1B step ramp up time from 2us to 4us/25mV */
90 pmic_reg_write(dev, PFUZE3000_SW1BCONF, 0x40);
92 /* SW1B mode to APS/PFM */
93 pmic_reg_write(dev, PFUZE3000_SW1BMODE, 0xc);
95 /* SW1B standby voltage set to 0.975V */
96 pmic_reg_write(dev, PFUZE3000_SW1BSTBY, 0xb);
104 gd->ram_size = imx_ddr_size();
109 static iomux_v3_cfg_t const uart1_pads[] = {
110 MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
111 MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
114 static iomux_v3_cfg_t const usdhc1_pads[] = {
115 MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
116 MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
117 MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
118 MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
119 MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
120 MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
123 MX6_PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
125 MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
127 MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
131 * mx6ul_14x14_evk board default supports sd card. If want to use
132 * EMMC, need to do board rework for sd2.
133 * Introduce CONFIG_MX6UL_14X14_EVK_EMMC_REWORK, if sd2 reworked to support
134 * emmc, need to define this macro.
136 #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
137 static iomux_v3_cfg_t const usdhc2_emmc_pads[] = {
138 MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
139 MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
140 MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
141 MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
142 MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
143 MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
144 MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
145 MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
146 MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
147 MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
152 MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
155 static iomux_v3_cfg_t const usdhc2_pads[] = {
156 MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
157 MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
158 MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
159 MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
160 MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
161 MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
165 * The evk board uses DAT3 to detect CD card plugin,
166 * in u-boot we mux the pin to GPIO when doing board_mmc_getcd.
168 static iomux_v3_cfg_t const usdhc2_cd_pad =
169 MX6_PAD_NAND_DATA03__GPIO4_IO05 | MUX_PAD_CTRL(USDHC_DAT3_CD_PAD_CTRL);
171 static iomux_v3_cfg_t const usdhc2_dat3_pad =
172 MX6_PAD_NAND_DATA03__USDHC2_DATA3 |
173 MUX_PAD_CTRL(USDHC_DAT3_CD_PAD_CTRL);
176 static void setup_iomux_uart(void)
178 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
181 #ifdef CONFIG_FSL_QSPI
182 static int board_qspi_init(void)
191 #ifdef CONFIG_FSL_ESDHC_IMX
192 static struct fsl_esdhc_cfg usdhc_cfg[2] = {
193 {USDHC1_BASE_ADDR, 0, 4},
194 #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
195 {USDHC2_BASE_ADDR, 0, 8},
197 {USDHC2_BASE_ADDR, 0, 4},
201 #define USDHC1_CD_GPIO IMX_GPIO_NR(1, 19)
202 #define USDHC1_PWR_GPIO IMX_GPIO_NR(1, 9)
203 #define USDHC2_CD_GPIO IMX_GPIO_NR(4, 5)
204 #define USDHC2_PWR_GPIO IMX_GPIO_NR(4, 10)
206 int board_mmc_getcd(struct mmc *mmc)
208 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
211 switch (cfg->esdhc_base) {
212 case USDHC1_BASE_ADDR:
213 ret = !gpio_get_value(USDHC1_CD_GPIO);
215 case USDHC2_BASE_ADDR:
216 #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
219 imx_iomux_v3_setup_pad(usdhc2_cd_pad);
220 gpio_request(USDHC2_CD_GPIO, "usdhc2 cd");
221 gpio_direction_input(USDHC2_CD_GPIO);
224 * Since it is the DAT3 pin, this pin is pulled to
225 * low voltage if no card
227 ret = gpio_get_value(USDHC2_CD_GPIO);
229 imx_iomux_v3_setup_pad(usdhc2_dat3_pad);
237 int board_mmc_init(bd_t *bis)
242 * According to the board_mmc_init() the following map is done:
243 * (U-Boot device node) (Physical Port)
247 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
250 imx_iomux_v3_setup_multiple_pads(
251 usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
252 gpio_request(USDHC1_CD_GPIO, "usdhc1 cd");
253 gpio_direction_input(USDHC1_CD_GPIO);
254 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
256 gpio_direction_output(USDHC1_PWR_GPIO, 0);
258 gpio_direction_output(USDHC1_PWR_GPIO, 1);
261 #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
262 imx_iomux_v3_setup_multiple_pads(
263 usdhc2_emmc_pads, ARRAY_SIZE(usdhc2_emmc_pads));
265 imx_iomux_v3_setup_multiple_pads(
266 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
268 gpio_request(USDHC2_PWR_GPIO, "usdhc2 pwr");
269 gpio_direction_output(USDHC2_PWR_GPIO, 0);
271 gpio_direction_output(USDHC2_PWR_GPIO, 1);
272 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
275 printf("Warning: you configured more USDHC controllers (%d) than supported by the board\n", i + 1);
279 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
281 printf("Warning: failed to initialize mmc dev %d\n", i);
289 #ifdef CONFIG_USB_EHCI_MX6
290 #ifndef CONFIG_DM_USB
292 #define USB_OTHERREGS_OFFSET 0x800
293 #define UCTRL_PWR_POL (1 << 9)
295 static iomux_v3_cfg_t const usb_otg_pads[] = {
296 MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
299 /* At default the 3v3 enables the MIC2026 for VBUS power */
300 static void setup_usb(void)
302 imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
303 ARRAY_SIZE(usb_otg_pads));
306 int board_usb_phy_mode(int port)
309 return USB_INIT_HOST;
311 return usb_phy_mode(port);
314 int board_ehci_hcd_init(int port)
321 usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
324 /* Set Power polarity */
325 setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
332 #ifdef CONFIG_FEC_MXC
334 * pin conflicts for fec1 and fec2, GPIO1_IO06 and GPIO1_IO07 can only
335 * be used for ENET1 or ENET2, cannot be used for both.
337 static iomux_v3_cfg_t const fec1_pads[] = {
338 MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
339 MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
340 MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
341 MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
342 MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
343 MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
344 MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
345 MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
346 MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
347 MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
350 static iomux_v3_cfg_t const fec2_pads[] = {
351 MX6_PAD_GPIO1_IO06__ENET2_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
352 MX6_PAD_GPIO1_IO07__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
354 MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
355 MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
356 MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
357 MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
359 MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
360 MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
361 MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
362 MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
365 static void setup_iomux_fec(int fec_id)
368 imx_iomux_v3_setup_multiple_pads(fec1_pads,
369 ARRAY_SIZE(fec1_pads));
371 imx_iomux_v3_setup_multiple_pads(fec2_pads,
372 ARRAY_SIZE(fec2_pads));
375 int board_eth_init(bd_t *bis)
377 setup_iomux_fec(CONFIG_FEC_ENET_DEV);
379 return fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV,
380 CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
383 static int setup_fec(int fec_id)
385 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
390 * Use 50M anatop loopback REF_CLK1 for ENET1,
391 * clear gpr1[13], set gpr1[17].
393 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
394 IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
397 * Use 50M anatop loopback REF_CLK2 for ENET2,
398 * clear gpr1[14], set gpr1[18].
400 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
401 IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
404 ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ);
413 int board_phy_config(struct phy_device *phydev)
415 phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
417 if (phydev->drv->config)
418 phydev->drv->config(phydev);
424 #ifdef CONFIG_DM_VIDEO
425 static iomux_v3_cfg_t const lcd_pads[] = {
426 /* Use GPIO for Brightness adjustment, duty cycle = period. */
427 MX6_PAD_GPIO1_IO08__GPIO1_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
430 static int setup_lcd(void)
432 enable_lcdif_clock(LCDIF1_BASE_ADDR, 1);
434 imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
437 gpio_request(IMX_GPIO_NR(5, 9), "lcd reset");
438 gpio_direction_output(IMX_GPIO_NR(5, 9) , 0);
440 gpio_direction_output(IMX_GPIO_NR(5, 9) , 1);
442 /* Set Brightness to high */
443 gpio_request(IMX_GPIO_NR(1, 8), "backlight");
444 gpio_direction_output(IMX_GPIO_NR(1, 8) , 1);
449 static inline int setup_lcd(void) { return 0; }
452 int board_early_init_f(void)
461 /* Address of boot parameters */
462 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
464 #ifdef CONFIG_FEC_MXC
465 setup_fec(CONFIG_FEC_ENET_DEV);
468 #ifdef CONFIG_USB_EHCI_MX6
469 #ifndef CONFIG_DM_USB
474 #ifdef CONFIG_FSL_QSPI
481 #ifdef CONFIG_CMD_BMODE
482 static const struct boot_mode board_boot_modes[] = {
483 /* 4 bit bus width */
484 {"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)},
485 {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
486 {"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
491 int board_late_init(void)
493 #ifdef CONFIG_CMD_BMODE
494 add_board_boot_modes(board_boot_modes);
497 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
498 env_set("board_name", "EVK");
500 if (is_mx6ul_9x9_evk())
501 env_set("board_rev", "9X9");
503 env_set("board_rev", "14X14");
513 if (is_mx6ul_9x9_evk())
514 puts("Board: MX6UL 9x9 EVK\n");
516 puts("Board: MX6UL 14x14 EVK\n");
521 #ifdef CONFIG_SPL_BUILD
522 #include <linux/libfdt.h>
524 #include <asm/arch/mx6-ddr.h>
527 static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
528 .grp_addds = 0x00000030,
529 .grp_ddrmode_ctl = 0x00020000,
530 .grp_b0ds = 0x00000030,
531 .grp_ctlds = 0x00000030,
532 .grp_b1ds = 0x00000030,
533 .grp_ddrpke = 0x00000000,
534 .grp_ddrmode = 0x00020000,
535 #ifdef CONFIG_TARGET_MX6UL_9X9_EVK
536 .grp_ddr_type = 0x00080000,
538 .grp_ddr_type = 0x000c0000,
542 #ifdef CONFIG_TARGET_MX6UL_9X9_EVK
543 static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
544 .dram_dqm0 = 0x00000030,
545 .dram_dqm1 = 0x00000030,
546 .dram_ras = 0x00000030,
547 .dram_cas = 0x00000030,
548 .dram_odt0 = 0x00000000,
549 .dram_odt1 = 0x00000000,
550 .dram_sdba2 = 0x00000000,
551 .dram_sdclk_0 = 0x00000030,
552 .dram_sdqs0 = 0x00003030,
553 .dram_sdqs1 = 0x00003030,
554 .dram_reset = 0x00000030,
557 static struct mx6_mmdc_calibration mx6_mmcd_calib = {
558 .p0_mpwldectrl0 = 0x00000000,
559 .p0_mpdgctrl0 = 0x20000000,
560 .p0_mprddlctl = 0x4040484f,
561 .p0_mpwrdlctl = 0x40405247,
562 .mpzqlp2ctl = 0x1b4700c7,
565 static struct mx6_lpddr2_cfg mem_ddr = {
578 struct mx6_ddr_sysinfo ddr_sysinfo = {
587 .rtt_wr = 0, /* LPDDR2 does not need rtt_wr rtt_nom */
589 .sde_to_rst = 0, /* LPDDR2 does not need this field */
590 .rst_to_cke = 0x10, /* JEDEC value for LPDDR2: 200us */
591 .ddr_type = DDR_TYPE_LPDDR2,
592 .refsel = 0, /* Refresh cycles at 64KHz */
593 .refr = 3, /* 4 refresh commands per refresh cycle */
597 static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
598 .dram_dqm0 = 0x00000030,
599 .dram_dqm1 = 0x00000030,
600 .dram_ras = 0x00000030,
601 .dram_cas = 0x00000030,
602 .dram_odt0 = 0x00000030,
603 .dram_odt1 = 0x00000030,
604 .dram_sdba2 = 0x00000000,
605 .dram_sdclk_0 = 0x00000030,
606 .dram_sdqs0 = 0x00000030,
607 .dram_sdqs1 = 0x00000030,
608 .dram_reset = 0x00000030,
611 static struct mx6_mmdc_calibration mx6_mmcd_calib = {
612 .p0_mpwldectrl0 = 0x00000000,
613 .p0_mpdgctrl0 = 0x41570155,
614 .p0_mprddlctl = 0x4040474A,
615 .p0_mpwrdlctl = 0x40405550,
618 struct mx6_ddr_sysinfo ddr_sysinfo = {
624 .rtt_nom = 1, /* RTT_Nom = RZQ/2 */
625 .walat = 0, /* Write additional latency */
626 .ralat = 5, /* Read additional latency */
627 .mif3_mode = 3, /* Command prediction working mode */
628 .bi_on = 1, /* Bank interleaving enabled */
629 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
630 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
631 .ddr_type = DDR_TYPE_DDR3,
632 .refsel = 0, /* Refresh cycles at 64KHz */
633 .refr = 1, /* 2 refresh commands per refresh cycle */
636 static struct mx6_ddr3_cfg mem_ddr = {
650 static void ccgr_init(void)
652 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
654 writel(0xFFFFFFFF, &ccm->CCGR0);
655 writel(0xFFFFFFFF, &ccm->CCGR1);
656 writel(0xFFFFFFFF, &ccm->CCGR2);
657 writel(0xFFFFFFFF, &ccm->CCGR3);
658 writel(0xFFFFFFFF, &ccm->CCGR4);
659 writel(0xFFFFFFFF, &ccm->CCGR5);
660 writel(0xFFFFFFFF, &ccm->CCGR6);
661 writel(0xFFFFFFFF, &ccm->CCGR7);
664 static void spl_dram_init(void)
666 mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
667 mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
670 void board_init_f(ulong dummy)
674 /* setup AIPS and disable watchdog */
677 /* iomux and setup of i2c */
678 board_early_init_f();
683 /* UART clocks enabled and gd valid - init serial console */
684 preloader_console_init();
686 /* DDR initialization */
690 memset(__bss_start, 0, __bss_end - __bss_start);
692 /* load/boot image from boot device */
693 board_init_r(NULL, 0);