2 * Copyright (C) 2014 Freescale Semiconductor, Inc.
4 * Author: Fabio Estevam <fabio.estevam@freescale.com>
6 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/clock.h>
10 #include <asm/arch/iomux.h>
11 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/mx6-pins.h>
13 #include <asm/arch/sys_proto.h>
15 #include <asm/imx-common/iomux-v3.h>
17 #include <asm/imx-common/mxc_i2c.h>
18 #include <linux/sizes.h>
20 #include <fsl_esdhc.h>
23 #include <power/pmic.h>
24 #include <power/pfuze100_pmic.h>
26 DECLARE_GLOBAL_DATA_PTR;
28 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
29 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
30 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
32 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
33 PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
34 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
36 #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
37 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
38 PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
43 gd->ram_size = PHYS_SDRAM_SIZE;
48 static iomux_v3_cfg_t const uart1_pads[] = {
49 MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
50 MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
53 static iomux_v3_cfg_t const usdhc4_pads[] = {
54 MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
55 MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
56 MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
57 MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
58 MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
59 MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
60 MX6_PAD_SD4_DATA7__GPIO6_IO_21 | MUX_PAD_CTRL(NO_PAD_CTRL),
63 static void setup_iomux_uart(void)
65 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
68 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
70 struct i2c_pads_info i2c_pad_info1 = {
72 .i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC,
73 .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC,
74 .gp = IMX_GPIO_NR(1, 0),
77 .i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC,
78 .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC,
79 .gp = IMX_GPIO_NR(1, 1),
83 static int pfuze_init(void)
89 ret = power_pfuze100_init(I2C_PMIC);
93 p = pmic_get("PFUZE100_PMIC");
98 pmic_reg_read(p, PFUZE100_DEVICEID, ®);
99 printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
101 /* Set SW1AB standby voltage to 0.975V */
102 pmic_reg_read(p, PFUZE100_SW1ABSTBY, ®);
105 pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
107 /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
108 pmic_reg_read(p, PUZE_100_SW1ABCONF, ®);
111 pmic_reg_write(p, PUZE_100_SW1ABCONF, reg);
113 /* Set SW1C standby voltage to 0.975V */
114 pmic_reg_read(p, PFUZE100_SW1CSTBY, ®);
117 pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
119 /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
120 pmic_reg_read(p, PFUZE100_SW1CCONF, ®);
123 pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
125 /* Enable power of VGEN5 3V3, needed for SD3 */
126 pmic_reg_read(p, PFUZE100_VGEN5VOL, ®);
129 pmic_reg_write(p, PFUZE100_VGEN5VOL, reg);
134 int board_early_init_f(void)
137 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
142 static struct fsl_esdhc_cfg usdhc_cfg[1] = {
146 int board_mmc_getcd(struct mmc *mmc)
148 return 1; /* Assume boot SD always present */
151 int board_mmc_init(bd_t *bis)
153 imx_iomux_v3_setup_multiple_pads(usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
155 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
156 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
161 /* Address of boot parameters */
162 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
167 int board_late_init(void)
176 puts("Board: MX6SX SABRE SDB\n");