board/freescale/mx6sxsabresd/mx6sxsabresd.c

   1 /*
   2  * Copyright (C) 2014 Freescale Semiconductor, Inc.
   3  *
   4  * Author: Fabio Estevam <fabio.estevam@freescale.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <asm/arch/clock.h>
  10 #include <asm/arch/iomux.h>
  11 #include <asm/arch/imx-regs.h>
  12 #include <asm/arch/mx6-pins.h>
  13 #include <asm/arch/sys_proto.h>
  14 #include <asm/gpio.h>
  15 #include <asm/imx-common/iomux-v3.h>
  16 #include <asm/io.h>
  17 #include <linux/sizes.h>
  18 #include <common.h>
  19 #include <fsl_esdhc.h>
  20 #include <mmc.h>
  21
  22 DECLARE_GLOBAL_DATA_PTR;
  23
  24 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
  25         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  26         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  27
  28 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |             \
  29         PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |               \
  30         PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  31
  32 int dram_init(void)
  33 {
  34         gd->ram_size = PHYS_SDRAM_SIZE;
  35
  36         return 0;
  37 }
  38
  39 static iomux_v3_cfg_t const uart1_pads[] = {
  40         MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  41         MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  42 };
  43
  44 static iomux_v3_cfg_t const usdhc4_pads[] = {
  45         MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  46         MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  47         MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  48         MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  49         MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  50         MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  51         MX6_PAD_SD4_DATA7__GPIO6_IO_21 | MUX_PAD_CTRL(NO_PAD_CTRL),
  52 };
  53
  54 static void setup_iomux_uart(void)
  55 {
  56         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
  57 }
  58
  59 int board_early_init_f(void)
  60 {
  61         setup_iomux_uart();
  62         return 0;
  63 }
  64
  65 static struct fsl_esdhc_cfg usdhc_cfg[1] = {
  66         {USDHC4_BASE_ADDR},
  67 };
  68
  69 int board_mmc_getcd(struct mmc *mmc)
  70 {
  71         return 1;       /* Assume boot SD always present */
  72 }
  73
  74 int board_mmc_init(bd_t *bis)
  75 {
  76         imx_iomux_v3_setup_multiple_pads(usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
  77
  78         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
  79         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
  80 }
  81
  82 int board_init(void)
  83 {
  84         /* Address of boot parameters */
  85         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  86
  87         return 0;
  88 }
  89
  90 int checkboard(void)
  91 {
  92         puts("Board: MX6SX SABRE SDB\n");
  93
  94         return 0;
  95 }