2 * Copyright (C) 2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
15 * Boot Device : one of
16 * spi/sd/nand/onenand, qspi/nor
22 * Device Configuration Data (DCD)
24 * Each entry must have the format:
25 * Addr-type Address Value
28 * Addr-type register length (1,2 or 4 bytes)
29 * Address absolute address of the register
30 * value value to be stored in the register
33 /* Enable all clocks */
34 DATA 4 0x020c4068 0xffffffff
35 DATA 4 0x020c406c 0xffffffff
36 DATA 4 0x020c4070 0xffffffff
37 DATA 4 0x020c4074 0xffffffff
38 DATA 4 0x020c4078 0xffffffff
39 DATA 4 0x020c407c 0xffffffff
40 DATA 4 0x020c4080 0xffffffff
41 DATA 4 0x020c4084 0xffffffff
43 /* IOMUX - DDR IO Type */
44 DATA 4 0x020e0618 0x000c0000
45 DATA 4 0x020e05fc 0x00000000
48 DATA 4 0x020e032c 0x00000030
51 DATA 4 0x020e0300 0x00000020
52 DATA 4 0x020e02fc 0x00000020
53 DATA 4 0x020e05f4 0x00000020
56 DATA 4 0x020e0340 0x00000020
58 DATA 4 0x020e0320 0x00000000
59 DATA 4 0x020e0310 0x00000020
60 DATA 4 0x020e0314 0x00000020
61 DATA 4 0x020e0614 0x00000020
64 DATA 4 0x020e05f8 0x00020000
65 DATA 4 0x020e0330 0x00000028
66 DATA 4 0x020e0334 0x00000028
67 DATA 4 0x020e0338 0x00000028
68 DATA 4 0x020e033c 0x00000028
71 DATA 4 0x020e0608 0x00020000
72 DATA 4 0x020e060c 0x00000028
73 DATA 4 0x020e0610 0x00000028
74 DATA 4 0x020e061c 0x00000028
75 DATA 4 0x020e0620 0x00000028
76 DATA 4 0x020e02ec 0x00000028
77 DATA 4 0x020e02f0 0x00000028
78 DATA 4 0x020e02f4 0x00000028
79 DATA 4 0x020e02f8 0x00000028
81 /* Calibrations - ZQ */
82 DATA 4 0x021b0800 0xa1390003
85 DATA 4 0x021b080c 0x00290025
86 DATA 4 0x021b0810 0x00220022
89 DATA 4 0x021b083c 0x41480144
90 DATA 4 0x021b0840 0x01340130
92 /* Read/Write Delay */
93 DATA 4 0x021b0848 0x3C3E4244
94 DATA 4 0x021b0850 0x34363638
96 /* Read data bit delay */
97 DATA 4 0x021b081c 0x33333333
98 DATA 4 0x021b0820 0x33333333
99 DATA 4 0x021b0824 0x33333333
100 DATA 4 0x021b0828 0x33333333
102 /* Complete calibration by forced measurement */
103 DATA 4 0x021b08b8 0x00000800
105 /* MMDC init - DDR3, 64-bit mode, only MMDC0 is initiated */
106 DATA 4 0x021b0004 0x0002002d
107 DATA 4 0x021b0008 0x00333030
108 DATA 4 0x021b000c 0x676b52f3
109 DATA 4 0x021b0010 0xb66d8b63
110 DATA 4 0x021b0014 0x01ff00db
111 DATA 4 0x021b0018 0x00011740
112 DATA 4 0x021b001c 0x00008000
113 DATA 4 0x021b002c 0x000026d2
114 DATA 4 0x021b0030 0x006b1023
115 DATA 4 0x021b0040 0x0000005f
116 DATA 4 0x021b0000 0x84190000
118 /* Initialize MT41K256M16HA-125 - MR2 */
119 DATA 4 0x021b001c 0x04008032
121 DATA 4 0x021b001c 0x00008033
123 DATA 4 0x021b001c 0x00048031
125 DATA 4 0x021b001c 0x05208030
126 /* DDR device ZQ calibration */
127 DATA 4 0x021b001c 0x04008040
129 /* Final DDR setup, before operation start */
130 DATA 4 0x021b0020 0x00000800
131 DATA 4 0x021b0818 0x00011117
132 DATA 4 0x021b001c 0x00000000