2 * Copyright (C) 2012 Freescale Semiconductor, Inc.
4 * Author: Fabio Estevam <fabio.estevam@freescale.com>
6 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/clock.h>
10 #include <asm/arch/imx-regs.h>
11 #include <asm/arch/iomux.h>
12 #include <asm/arch/mx6-pins.h>
13 #include <asm/errno.h>
15 #include <asm/imx-common/iomux-v3.h>
16 #include <asm/imx-common/boot_mode.h>
18 #include <fsl_esdhc.h>
21 #include <asm/arch/mxc_hdmi.h>
22 #include <asm/arch/crm_regs.h>
24 #include <ipu_pixfmt.h>
26 #include <asm/arch/sys_proto.h>
27 DECLARE_GLOBAL_DATA_PTR;
29 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
30 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
31 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
33 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
34 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
35 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
37 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
38 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
42 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
47 iomux_v3_cfg_t const uart1_pads[] = {
48 MX6_PAD_CSI0_DAT10__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
49 MX6_PAD_CSI0_DAT11__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
52 iomux_v3_cfg_t const enet_pads[] = {
53 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
54 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
55 MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
56 MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
57 MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
58 MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
59 MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
60 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
61 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
62 MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
63 MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
64 MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
65 MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
66 MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
67 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
68 /* AR8031 PHY Reset */
69 MX6_PAD_ENET_CRS_DV__GPIO_1_25 | MUX_PAD_CTRL(NO_PAD_CTRL),
72 static void setup_iomux_enet(void)
74 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
76 /* Reset AR8031 PHY */
77 gpio_direction_output(IMX_GPIO_NR(1, 25) , 0);
79 gpio_set_value(IMX_GPIO_NR(1, 25), 1);
82 iomux_v3_cfg_t const usdhc2_pads[] = {
83 MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
84 MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
85 MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
86 MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
87 MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
88 MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
89 MX6_PAD_NANDF_D4__USDHC2_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
90 MX6_PAD_NANDF_D5__USDHC2_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
91 MX6_PAD_NANDF_D6__USDHC2_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
92 MX6_PAD_NANDF_D7__USDHC2_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
93 MX6_PAD_NANDF_D2__GPIO_2_2 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
96 iomux_v3_cfg_t const usdhc3_pads[] = {
97 MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
98 MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
99 MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
100 MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
101 MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
102 MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
103 MX6_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
104 MX6_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
105 MX6_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
106 MX6_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
107 MX6_PAD_NANDF_D0__GPIO_2_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
110 iomux_v3_cfg_t const usdhc4_pads[] = {
111 MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
112 MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
113 MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
114 MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
115 MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
116 MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
117 MX6_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
118 MX6_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
119 MX6_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
120 MX6_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
123 static void setup_iomux_uart(void)
125 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
128 #ifdef CONFIG_FSL_ESDHC
129 struct fsl_esdhc_cfg usdhc_cfg[3] = {
135 #define USDHC2_CD_GPIO IMX_GPIO_NR(2, 2)
136 #define USDHC3_CD_GPIO IMX_GPIO_NR(2, 0)
138 int board_mmc_getcd(struct mmc *mmc)
140 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
143 switch (cfg->esdhc_base) {
144 case USDHC2_BASE_ADDR:
145 ret = !gpio_get_value(USDHC2_CD_GPIO);
147 case USDHC3_BASE_ADDR:
148 ret = !gpio_get_value(USDHC3_CD_GPIO);
150 case USDHC4_BASE_ADDR:
151 ret = 1; /* eMMC/uSDHC4 is always present */
158 int board_mmc_init(bd_t *bis)
164 * According to the board_mmc_init() the following map is done:
165 * (U-boot device node) (Physical Port)
170 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
173 imx_iomux_v3_setup_multiple_pads(
174 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
175 gpio_direction_input(USDHC2_CD_GPIO);
176 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
179 imx_iomux_v3_setup_multiple_pads(
180 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
181 gpio_direction_input(USDHC3_CD_GPIO);
182 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
185 imx_iomux_v3_setup_multiple_pads(
186 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
187 usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
190 printf("Warning: you configured more USDHC controllers"
191 "(%d) then supported by the board (%d)\n",
192 i + 1, CONFIG_SYS_FSL_USDHC_NUM);
196 status |= fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
203 int mx6_rgmii_rework(struct phy_device *phydev)
207 /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
208 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
209 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
210 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
212 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
215 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
217 /* introduce tx clock delay */
218 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
219 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
221 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
226 int board_phy_config(struct phy_device *phydev)
228 mx6_rgmii_rework(phydev);
230 if (phydev->drv->config)
231 phydev->drv->config(phydev);
236 #if defined(CONFIG_VIDEO_IPUV3)
237 struct display_info_t {
241 int (*detect)(struct display_info_t const *dev);
242 void (*enable)(struct display_info_t const *dev);
243 struct fb_videomode mode;
246 static int detect_hdmi(struct display_info_t const *dev)
248 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
249 return readb(&hdmi->phy_stat0) & HDMI_DVI_STAT;
252 static void do_enable_hdmi(struct display_info_t const *dev)
254 imx_enable_hdmi_phy();
257 static void enable_lvds(struct display_info_t const *dev)
259 struct iomuxc *iomux = (struct iomuxc *)
261 u32 reg = readl(&iomux->gpr[2]);
262 reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
263 IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT;
264 writel(reg, &iomux->gpr[2]);
266 static struct display_info_t const displays[] = {{
269 .pixfmt = IPU_PIX_FMT_RGB24,
270 .detect = detect_hdmi,
271 .enable = do_enable_hdmi,
285 .vmode = FB_VMODE_NONINTERLACED
289 .pixfmt = IPU_PIX_FMT_LVDS666,
291 .enable = enable_lvds,
293 .name = "Hannstar-XGA",
305 .vmode = FB_VMODE_NONINTERLACED
308 int board_video_skip(void)
312 char const *panel = getenv("panel");
314 for (i = 0; i < ARRAY_SIZE(displays); i++) {
315 struct display_info_t const *dev = displays+i;
316 if (dev->detect(dev)) {
317 panel = dev->mode.name;
318 printf("auto-detected panel %s\n", panel);
323 panel = displays[0].mode.name;
324 printf("No panel detected: default to %s\n", panel);
327 for (i = 0; i < ARRAY_SIZE(displays); i++) {
328 if (!strcmp(panel, displays[i].mode.name))
332 if (i < ARRAY_SIZE(displays)) {
333 ret = ipuv3_fb_init(&displays[i].mode, 0,
336 displays[i].enable(displays+i);
337 printf("Display: %s (%ux%u)\n",
338 displays[i].mode.name,
339 displays[i].mode.xres,
340 displays[i].mode.yres);
342 printf("LCD %s cannot be configured: %d\n",
343 displays[i].mode.name, ret);
345 printf("unsupported panel %s\n", panel);
352 static void setup_display(void)
354 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
355 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
361 /* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */
362 reg = __raw_readl(&mxc_ccm->CCGR3);
363 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
364 writel(reg, &mxc_ccm->CCGR3);
366 /* set LDB0, LDB1 clk select to 011/011 */
367 reg = readl(&mxc_ccm->cs2cdr);
368 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
369 | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
370 reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
371 | (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
372 writel(reg, &mxc_ccm->cs2cdr);
374 reg = readl(&mxc_ccm->cscmr2);
375 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
376 writel(reg, &mxc_ccm->cscmr2);
378 reg = readl(&mxc_ccm->chsccdr);
379 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
380 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
381 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
382 << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
383 writel(reg, &mxc_ccm->chsccdr);
385 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
386 | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW
387 | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
388 | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
389 | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
390 | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
391 | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
392 | IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED
393 | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0;
394 writel(reg, &iomux->gpr[2]);
396 reg = readl(&iomux->gpr[3]);
397 reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK
398 | IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
399 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
400 << IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET);
401 writel(reg, &iomux->gpr[3]);
403 #endif /* CONFIG_VIDEO_IPUV3 */
406 * Do not overwrite the console
407 * Use always serial for U-Boot console
409 int overwrite_console(void)
414 int board_eth_init(bd_t *bis)
420 ret = cpu_eth_init(bis);
422 printf("FEC MXC: %s:failed\n", __func__);
427 int board_early_init_f(void)
430 #if defined(CONFIG_VIDEO_IPUV3)
439 /* address of boot parameters */
440 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
445 #ifdef CONFIG_CMD_BMODE
446 static const struct boot_mode board_boot_modes[] = {
447 /* 4 bit bus width */
448 {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
449 {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
450 /* 8 bit bus width */
451 {"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
456 int board_late_init(void)
458 #ifdef CONFIG_CMD_BMODE
459 add_board_boot_modes(board_boot_modes);
467 puts("Board: MX6-SabreSD\n");