2 * Copyright (C) 2012 Freescale Semiconductor, Inc.
4 * Author: Fabio Estevam <fabio.estevam@freescale.com>
6 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/clock.h>
10 #include <asm/arch/imx-regs.h>
11 #include <asm/arch/iomux.h>
12 #include <asm/arch/mx6-pins.h>
13 #include <asm/errno.h>
15 #include <asm/imx-common/mxc_i2c.h>
16 #include <asm/imx-common/iomux-v3.h>
17 #include <asm/imx-common/boot_mode.h>
18 #include <asm/imx-common/video.h>
20 #include <fsl_esdhc.h>
23 #include <asm/arch/mxc_hdmi.h>
24 #include <asm/arch/crm_regs.h>
26 #include <asm/arch/sys_proto.h>
28 #include <power/pmic.h>
29 #include <power/pfuze100_pmic.h>
30 DECLARE_GLOBAL_DATA_PTR;
32 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
33 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
34 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
36 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
37 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
38 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
40 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
41 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
43 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
44 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
46 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
47 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
48 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
52 #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
54 #define DISP0_PWR_EN IMX_GPIO_NR(1, 21)
58 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
63 iomux_v3_cfg_t const uart1_pads[] = {
64 MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
65 MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
68 iomux_v3_cfg_t const enet_pads[] = {
69 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
70 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
71 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
72 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
73 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
74 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
75 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
76 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
77 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
78 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
79 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
80 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
81 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
82 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
83 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
84 /* AR8031 PHY Reset */
85 MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
88 static void setup_iomux_enet(void)
90 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
92 /* Reset AR8031 PHY */
93 gpio_direction_output(IMX_GPIO_NR(1, 25) , 0);
95 gpio_set_value(IMX_GPIO_NR(1, 25), 1);
98 iomux_v3_cfg_t const usdhc2_pads[] = {
99 MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
100 MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
101 MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
102 MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
103 MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
104 MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
105 MX6_PAD_NANDF_D4__SD2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
106 MX6_PAD_NANDF_D5__SD2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
107 MX6_PAD_NANDF_D6__SD2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
108 MX6_PAD_NANDF_D7__SD2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
109 MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
112 iomux_v3_cfg_t const usdhc3_pads[] = {
113 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
114 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
115 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
116 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
117 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
118 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
119 MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
120 MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
121 MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
122 MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
123 MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
126 iomux_v3_cfg_t const usdhc4_pads[] = {
127 MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
128 MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
129 MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
130 MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
131 MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
132 MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
133 MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
134 MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
135 MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
136 MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
139 iomux_v3_cfg_t const ecspi1_pads[] = {
140 MX6_PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
141 MX6_PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
142 MX6_PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
143 MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
146 static iomux_v3_cfg_t const rgb_pads[] = {
147 MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL),
148 MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL),
149 MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(NO_PAD_CTRL),
150 MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(NO_PAD_CTRL),
151 MX6_PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(NO_PAD_CTRL),
152 MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL),
153 MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL),
154 MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL),
155 MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL),
156 MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL),
157 MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL),
158 MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL),
159 MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL),
160 MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(NO_PAD_CTRL),
161 MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(NO_PAD_CTRL),
162 MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(NO_PAD_CTRL),
163 MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(NO_PAD_CTRL),
164 MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(NO_PAD_CTRL),
165 MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(NO_PAD_CTRL),
166 MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(NO_PAD_CTRL),
167 MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(NO_PAD_CTRL),
168 MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(NO_PAD_CTRL),
169 MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(NO_PAD_CTRL),
170 MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 | MUX_PAD_CTRL(NO_PAD_CTRL),
171 MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 | MUX_PAD_CTRL(NO_PAD_CTRL),
172 MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 | MUX_PAD_CTRL(NO_PAD_CTRL),
173 MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 | MUX_PAD_CTRL(NO_PAD_CTRL),
174 MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 | MUX_PAD_CTRL(NO_PAD_CTRL),
175 MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 | MUX_PAD_CTRL(NO_PAD_CTRL),
176 MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
179 static void enable_rgb(struct display_info_t const *dev)
181 imx_iomux_v3_setup_multiple_pads(rgb_pads, ARRAY_SIZE(rgb_pads));
182 gpio_direction_output(DISP0_PWR_EN, 1);
185 static struct i2c_pads_info i2c_pad_info1 = {
187 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
188 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
189 .gp = IMX_GPIO_NR(4, 12)
192 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
193 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
194 .gp = IMX_GPIO_NR(4, 13)
198 static void setup_spi(void)
200 imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
203 iomux_v3_cfg_t const pcie_pads[] = {
204 MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), /* POWER */
205 MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL), /* RESET */
208 static void setup_pcie(void)
210 imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
213 iomux_v3_cfg_t const di0_pads[] = {
214 MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* DISP0_CLK */
215 MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, /* DISP0_HSYNC */
216 MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, /* DISP0_VSYNC */
219 static void setup_iomux_uart(void)
221 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
224 #ifdef CONFIG_FSL_ESDHC
225 struct fsl_esdhc_cfg usdhc_cfg[3] = {
231 #define USDHC2_CD_GPIO IMX_GPIO_NR(2, 2)
232 #define USDHC3_CD_GPIO IMX_GPIO_NR(2, 0)
234 int board_mmc_getcd(struct mmc *mmc)
236 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
239 switch (cfg->esdhc_base) {
240 case USDHC2_BASE_ADDR:
241 ret = !gpio_get_value(USDHC2_CD_GPIO);
243 case USDHC3_BASE_ADDR:
244 ret = !gpio_get_value(USDHC3_CD_GPIO);
246 case USDHC4_BASE_ADDR:
247 ret = 1; /* eMMC/uSDHC4 is always present */
254 int board_mmc_init(bd_t *bis)
260 * According to the board_mmc_init() the following map is done:
261 * (U-boot device node) (Physical Port)
266 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
269 imx_iomux_v3_setup_multiple_pads(
270 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
271 gpio_direction_input(USDHC2_CD_GPIO);
272 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
275 imx_iomux_v3_setup_multiple_pads(
276 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
277 gpio_direction_input(USDHC3_CD_GPIO);
278 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
281 imx_iomux_v3_setup_multiple_pads(
282 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
283 usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
286 printf("Warning: you configured more USDHC controllers"
287 "(%d) then supported by the board (%d)\n",
288 i + 1, CONFIG_SYS_FSL_USDHC_NUM);
292 status |= fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
299 int mx6_rgmii_rework(struct phy_device *phydev)
303 /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
304 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
305 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
306 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
308 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
311 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
313 /* introduce tx clock delay */
314 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
315 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
317 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
322 int board_phy_config(struct phy_device *phydev)
324 mx6_rgmii_rework(phydev);
326 if (phydev->drv->config)
327 phydev->drv->config(phydev);
332 #if defined(CONFIG_VIDEO_IPUV3)
333 static void disable_lvds(struct display_info_t const *dev)
335 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
337 int reg = readl(&iomux->gpr[2]);
339 reg &= ~(IOMUXC_GPR2_LVDS_CH0_MODE_MASK |
340 IOMUXC_GPR2_LVDS_CH1_MODE_MASK);
342 writel(reg, &iomux->gpr[2]);
345 static void do_enable_hdmi(struct display_info_t const *dev)
348 imx_enable_hdmi_phy();
351 static void enable_lvds(struct display_info_t const *dev)
353 struct iomuxc *iomux = (struct iomuxc *)
355 u32 reg = readl(&iomux->gpr[2]);
356 reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
357 IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT;
358 writel(reg, &iomux->gpr[2]);
361 struct display_info_t const displays[] = {{
364 .pixfmt = IPU_PIX_FMT_RGB666,
366 .enable = enable_lvds,
368 .name = "Hannstar-XGA",
380 .vmode = FB_VMODE_NONINTERLACED
384 .pixfmt = IPU_PIX_FMT_RGB24,
385 .detect = detect_hdmi,
386 .enable = do_enable_hdmi,
400 .vmode = FB_VMODE_NONINTERLACED
404 .pixfmt = IPU_PIX_FMT_RGB24,
406 .enable = enable_rgb,
408 .name = "SEIKO-WVGA",
420 .vmode = FB_VMODE_NONINTERLACED
422 size_t display_count = ARRAY_SIZE(displays);
424 static void setup_display(void)
426 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
427 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
430 /* Setup HSYNC, VSYNC, DISP_CLK for debugging purposes */
431 imx_iomux_v3_setup_multiple_pads(di0_pads, ARRAY_SIZE(di0_pads));
436 /* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */
437 reg = readl(&mxc_ccm->CCGR3);
438 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
439 writel(reg, &mxc_ccm->CCGR3);
441 /* set LDB0, LDB1 clk select to 011/011 */
442 reg = readl(&mxc_ccm->cs2cdr);
443 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
444 | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
445 reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
446 | (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
447 writel(reg, &mxc_ccm->cs2cdr);
449 reg = readl(&mxc_ccm->cscmr2);
450 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
451 writel(reg, &mxc_ccm->cscmr2);
453 reg = readl(&mxc_ccm->chsccdr);
454 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
455 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
456 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
457 << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
458 writel(reg, &mxc_ccm->chsccdr);
460 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
461 | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW
462 | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
463 | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
464 | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
465 | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
466 | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
467 | IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED
468 | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0;
469 writel(reg, &iomux->gpr[2]);
471 reg = readl(&iomux->gpr[3]);
472 reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK
473 | IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
474 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
475 << IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET);
476 writel(reg, &iomux->gpr[3]);
478 #endif /* CONFIG_VIDEO_IPUV3 */
481 * Do not overwrite the console
482 * Use always serial for U-Boot console
484 int overwrite_console(void)
489 int board_eth_init(bd_t *bis)
494 return cpu_eth_init(bis);
497 int board_early_init_f(void)
500 #if defined(CONFIG_VIDEO_IPUV3)
509 /* address of boot parameters */
510 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
512 #ifdef CONFIG_MXC_SPI
515 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
520 static int pfuze_init(void)
526 ret = power_pfuze100_init(I2C_PMIC);
530 p = pmic_get("PFUZE100");
535 pmic_reg_read(p, PFUZE100_DEVICEID, ®);
536 printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
538 /* Increase VGEN3 from 2.5 to 2.8V */
539 pmic_reg_read(p, PFUZE100_VGEN3VOL, ®);
542 pmic_reg_write(p, PFUZE100_VGEN3VOL, reg);
544 /* Increase VGEN5 from 2.8 to 3V */
545 pmic_reg_read(p, PFUZE100_VGEN5VOL, ®);
548 pmic_reg_write(p, PFUZE100_VGEN5VOL, reg);
550 /* Set SW1AB stanby volage to 0.975V */
551 pmic_reg_read(p, PFUZE100_SW1ABSTBY, ®);
554 pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
556 /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
557 pmic_reg_read(p, PUZE_100_SW1ABCONF, ®);
560 pmic_reg_write(p, PUZE_100_SW1ABCONF, reg);
562 /* Set SW1C standby voltage to 0.975V */
563 pmic_reg_read(p, PFUZE100_SW1CSTBY, ®);
566 pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
568 /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
569 pmic_reg_read(p, PFUZE100_SW1CCONF, ®);
572 pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
577 #ifdef CONFIG_MXC_SPI
578 int board_spi_cs_gpio(unsigned bus, unsigned cs)
580 return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1;
584 #ifdef CONFIG_CMD_BMODE
585 static const struct boot_mode board_boot_modes[] = {
586 /* 4 bit bus width */
587 {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
588 {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
589 /* 8 bit bus width */
590 {"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
595 int board_late_init(void)
597 #ifdef CONFIG_CMD_BMODE
598 add_board_boot_modes(board_boot_modes);
607 puts("Board: MX6-SabreSD\n");