2 * Copyright (C) 2012 Freescale Semiconductor, Inc.
4 * Author: Fabio Estevam <fabio.estevam@freescale.com>
6 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/clock.h>
10 #include <asm/arch/imx-regs.h>
11 #include <asm/arch/iomux.h>
12 #include <asm/arch/mx6-pins.h>
13 #include <asm/errno.h>
15 #include <asm/imx-common/mxc_i2c.h>
16 #include <asm/imx-common/iomux-v3.h>
17 #include <asm/imx-common/boot_mode.h>
18 #include <asm/imx-common/video.h>
20 #include <fsl_esdhc.h>
23 #include <asm/arch/mxc_hdmi.h>
24 #include <asm/arch/crm_regs.h>
26 #include <asm/arch/sys_proto.h>
28 #include <power/pmic.h>
29 #include <power/pfuze100_pmic.h>
30 #include <asm/arch/mx6-ddr.h>
32 DECLARE_GLOBAL_DATA_PTR;
34 #define BOOT_CFG 0x020D8004
36 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
37 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
38 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
40 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
41 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
42 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
44 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
45 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
47 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
48 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
50 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
51 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
52 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
56 #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
58 #define DISP0_PWR_EN IMX_GPIO_NR(1, 21)
62 gd->ram_size = imx_ddr_size();
66 static iomux_v3_cfg_t const uart1_pads[] = {
67 MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
68 MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
71 static iomux_v3_cfg_t const enet_pads[] = {
72 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
73 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
74 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
75 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
76 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
77 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
78 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
79 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
80 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
81 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
82 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
83 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
84 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
85 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
86 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
87 /* AR8031 PHY Reset */
88 MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
91 static void setup_iomux_enet(void)
93 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
95 /* Reset AR8031 PHY */
96 gpio_direction_output(IMX_GPIO_NR(1, 25) , 0);
98 gpio_set_value(IMX_GPIO_NR(1, 25), 1);
101 static iomux_v3_cfg_t const usdhc2_pads[] = {
102 MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
103 MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
104 MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
105 MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
106 MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
107 MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
108 MX6_PAD_NANDF_D4__SD2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
109 MX6_PAD_NANDF_D5__SD2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
110 MX6_PAD_NANDF_D6__SD2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
111 MX6_PAD_NANDF_D7__SD2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
112 MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
115 static iomux_v3_cfg_t const usdhc3_pads[] = {
116 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
117 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
118 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
119 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
120 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
121 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
122 MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
123 MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
124 MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
125 MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
126 MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
129 static iomux_v3_cfg_t const usdhc4_pads[] = {
130 MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
131 MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
132 MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
133 MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
134 MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
135 MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
136 MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
137 MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
138 MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
139 MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
142 static iomux_v3_cfg_t const ecspi1_pads[] = {
143 MX6_PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
144 MX6_PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
145 MX6_PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
146 MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
149 static iomux_v3_cfg_t const rgb_pads[] = {
150 MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL),
151 MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL),
152 MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(NO_PAD_CTRL),
153 MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(NO_PAD_CTRL),
154 MX6_PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(NO_PAD_CTRL),
155 MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL),
156 MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL),
157 MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL),
158 MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL),
159 MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL),
160 MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL),
161 MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL),
162 MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL),
163 MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(NO_PAD_CTRL),
164 MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(NO_PAD_CTRL),
165 MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(NO_PAD_CTRL),
166 MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(NO_PAD_CTRL),
167 MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(NO_PAD_CTRL),
168 MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(NO_PAD_CTRL),
169 MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(NO_PAD_CTRL),
170 MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(NO_PAD_CTRL),
171 MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(NO_PAD_CTRL),
172 MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(NO_PAD_CTRL),
173 MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 | MUX_PAD_CTRL(NO_PAD_CTRL),
174 MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 | MUX_PAD_CTRL(NO_PAD_CTRL),
175 MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 | MUX_PAD_CTRL(NO_PAD_CTRL),
176 MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 | MUX_PAD_CTRL(NO_PAD_CTRL),
177 MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 | MUX_PAD_CTRL(NO_PAD_CTRL),
178 MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 | MUX_PAD_CTRL(NO_PAD_CTRL),
179 MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
182 static void enable_rgb(struct display_info_t const *dev)
184 imx_iomux_v3_setup_multiple_pads(rgb_pads, ARRAY_SIZE(rgb_pads));
185 gpio_direction_output(DISP0_PWR_EN, 1);
188 static struct i2c_pads_info i2c_pad_info1 = {
190 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
191 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
192 .gp = IMX_GPIO_NR(4, 12)
195 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
196 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
197 .gp = IMX_GPIO_NR(4, 13)
201 static void setup_spi(void)
203 imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
206 iomux_v3_cfg_t const pcie_pads[] = {
207 MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), /* POWER */
208 MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL), /* RESET */
211 static void setup_pcie(void)
213 imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
216 iomux_v3_cfg_t const di0_pads[] = {
217 MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* DISP0_CLK */
218 MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, /* DISP0_HSYNC */
219 MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, /* DISP0_VSYNC */
222 static void setup_iomux_uart(void)
224 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
227 #ifdef CONFIG_FSL_ESDHC
228 struct fsl_esdhc_cfg usdhc_cfg[3] = {
234 #define USDHC2_CD_GPIO IMX_GPIO_NR(2, 2)
235 #define USDHC3_CD_GPIO IMX_GPIO_NR(2, 0)
237 int board_mmc_getcd(struct mmc *mmc)
239 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
242 switch (cfg->esdhc_base) {
243 case USDHC2_BASE_ADDR:
244 ret = !gpio_get_value(USDHC2_CD_GPIO);
246 case USDHC3_BASE_ADDR:
247 ret = !gpio_get_value(USDHC3_CD_GPIO);
249 case USDHC4_BASE_ADDR:
250 ret = 1; /* eMMC/uSDHC4 is always present */
257 int board_mmc_init(bd_t *bis)
259 #ifndef CONFIG_SPL_BUILD
264 * According to the board_mmc_init() the following map is done:
265 * (U-boot device node) (Physical Port)
270 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
273 imx_iomux_v3_setup_multiple_pads(
274 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
275 gpio_direction_input(USDHC2_CD_GPIO);
276 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
279 imx_iomux_v3_setup_multiple_pads(
280 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
281 gpio_direction_input(USDHC3_CD_GPIO);
282 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
285 imx_iomux_v3_setup_multiple_pads(
286 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
287 usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
290 printf("Warning: you configured more USDHC controllers"
291 "(%d) then supported by the board (%d)\n",
292 i + 1, CONFIG_SYS_FSL_USDHC_NUM);
296 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
303 unsigned reg = readl(BOOT_CFG) >> 11;
305 * Upon reading BOOT_CFG register the following map is done:
306 * Bit 11 and 12 of BOOT_CFG register can determine the current
315 imx_iomux_v3_setup_multiple_pads(
316 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
317 usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
318 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
319 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
322 imx_iomux_v3_setup_multiple_pads(
323 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
324 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
325 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
326 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
329 imx_iomux_v3_setup_multiple_pads(
330 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
331 usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
332 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
333 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
337 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
342 int mx6_rgmii_rework(struct phy_device *phydev)
346 /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
347 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
348 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
349 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
351 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
354 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
356 /* introduce tx clock delay */
357 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
358 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
360 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
365 int board_phy_config(struct phy_device *phydev)
367 mx6_rgmii_rework(phydev);
369 if (phydev->drv->config)
370 phydev->drv->config(phydev);
375 #if defined(CONFIG_VIDEO_IPUV3)
376 static void disable_lvds(struct display_info_t const *dev)
378 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
380 int reg = readl(&iomux->gpr[2]);
382 reg &= ~(IOMUXC_GPR2_LVDS_CH0_MODE_MASK |
383 IOMUXC_GPR2_LVDS_CH1_MODE_MASK);
385 writel(reg, &iomux->gpr[2]);
388 static void do_enable_hdmi(struct display_info_t const *dev)
391 imx_enable_hdmi_phy();
394 static void enable_lvds(struct display_info_t const *dev)
396 struct iomuxc *iomux = (struct iomuxc *)
398 u32 reg = readl(&iomux->gpr[2]);
399 reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
400 IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT;
401 writel(reg, &iomux->gpr[2]);
404 struct display_info_t const displays[] = {{
407 .pixfmt = IPU_PIX_FMT_RGB666,
409 .enable = enable_lvds,
411 .name = "Hannstar-XGA",
423 .vmode = FB_VMODE_NONINTERLACED
427 .pixfmt = IPU_PIX_FMT_RGB24,
428 .detect = detect_hdmi,
429 .enable = do_enable_hdmi,
443 .vmode = FB_VMODE_NONINTERLACED
447 .pixfmt = IPU_PIX_FMT_RGB24,
449 .enable = enable_rgb,
451 .name = "SEIKO-WVGA",
463 .vmode = FB_VMODE_NONINTERLACED
465 size_t display_count = ARRAY_SIZE(displays);
467 static void setup_display(void)
469 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
470 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
473 /* Setup HSYNC, VSYNC, DISP_CLK for debugging purposes */
474 imx_iomux_v3_setup_multiple_pads(di0_pads, ARRAY_SIZE(di0_pads));
479 /* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */
480 reg = readl(&mxc_ccm->CCGR3);
481 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
482 writel(reg, &mxc_ccm->CCGR3);
484 /* set LDB0, LDB1 clk select to 011/011 */
485 reg = readl(&mxc_ccm->cs2cdr);
486 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
487 | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
488 reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
489 | (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
490 writel(reg, &mxc_ccm->cs2cdr);
492 reg = readl(&mxc_ccm->cscmr2);
493 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
494 writel(reg, &mxc_ccm->cscmr2);
496 reg = readl(&mxc_ccm->chsccdr);
497 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
498 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
499 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
500 << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
501 writel(reg, &mxc_ccm->chsccdr);
503 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
504 | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW
505 | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
506 | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
507 | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
508 | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
509 | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
510 | IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED
511 | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0;
512 writel(reg, &iomux->gpr[2]);
514 reg = readl(&iomux->gpr[3]);
515 reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK
516 | IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
517 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
518 << IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET);
519 writel(reg, &iomux->gpr[3]);
521 #endif /* CONFIG_VIDEO_IPUV3 */
524 * Do not overwrite the console
525 * Use always serial for U-Boot console
527 int overwrite_console(void)
532 int board_eth_init(bd_t *bis)
537 return cpu_eth_init(bis);
540 int board_early_init_f(void)
543 #if defined(CONFIG_VIDEO_IPUV3)
552 /* address of boot parameters */
553 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
555 #ifdef CONFIG_MXC_SPI
558 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
563 static int pfuze_init(void)
569 ret = power_pfuze100_init(I2C_PMIC);
573 p = pmic_get("PFUZE100");
578 pmic_reg_read(p, PFUZE100_DEVICEID, ®);
579 printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
581 /* Increase VGEN3 from 2.5 to 2.8V */
582 pmic_reg_read(p, PFUZE100_VGEN3VOL, ®);
585 pmic_reg_write(p, PFUZE100_VGEN3VOL, reg);
587 /* Increase VGEN5 from 2.8 to 3V */
588 pmic_reg_read(p, PFUZE100_VGEN5VOL, ®);
591 pmic_reg_write(p, PFUZE100_VGEN5VOL, reg);
593 /* Set SW1AB stanby volage to 0.975V */
594 pmic_reg_read(p, PFUZE100_SW1ABSTBY, ®);
597 pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
599 /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
600 pmic_reg_read(p, PUZE_100_SW1ABCONF, ®);
603 pmic_reg_write(p, PUZE_100_SW1ABCONF, reg);
605 /* Set SW1C standby voltage to 0.975V */
606 pmic_reg_read(p, PFUZE100_SW1CSTBY, ®);
609 pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
611 /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
612 pmic_reg_read(p, PFUZE100_SW1CCONF, ®);
615 pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
620 #ifdef CONFIG_MXC_SPI
621 int board_spi_cs_gpio(unsigned bus, unsigned cs)
623 return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1;
627 #ifdef CONFIG_CMD_BMODE
628 static const struct boot_mode board_boot_modes[] = {
629 /* 4 bit bus width */
630 {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
631 {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
632 /* 8 bit bus width */
633 {"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
638 int board_late_init(void)
640 #ifdef CONFIG_CMD_BMODE
641 add_board_boot_modes(board_boot_modes);
650 puts("Board: MX6-SabreSD\n");
654 #ifdef CONFIG_SPL_BUILD
658 const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
659 .dram_sdclk_0 = 0x00020030,
660 .dram_sdclk_1 = 0x00020030,
661 .dram_cas = 0x00020030,
662 .dram_ras = 0x00020030,
663 .dram_reset = 0x00020030,
664 .dram_sdcke0 = 0x00003000,
665 .dram_sdcke1 = 0x00003000,
666 .dram_sdba2 = 0x00000000,
667 .dram_sdodt0 = 0x00003030,
668 .dram_sdodt1 = 0x00003030,
669 .dram_sdqs0 = 0x00000030,
670 .dram_sdqs1 = 0x00000030,
671 .dram_sdqs2 = 0x00000030,
672 .dram_sdqs3 = 0x00000030,
673 .dram_sdqs4 = 0x00000030,
674 .dram_sdqs5 = 0x00000030,
675 .dram_sdqs6 = 0x00000030,
676 .dram_sdqs7 = 0x00000030,
677 .dram_dqm0 = 0x00020030,
678 .dram_dqm1 = 0x00020030,
679 .dram_dqm2 = 0x00020030,
680 .dram_dqm3 = 0x00020030,
681 .dram_dqm4 = 0x00020030,
682 .dram_dqm5 = 0x00020030,
683 .dram_dqm6 = 0x00020030,
684 .dram_dqm7 = 0x00020030,
687 const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
688 .grp_ddr_type = 0x000C0000,
689 .grp_ddrmode_ctl = 0x00020000,
690 .grp_ddrpke = 0x00000000,
691 .grp_addds = 0x00000030,
692 .grp_ctlds = 0x00000030,
693 .grp_ddrmode = 0x00020000,
694 .grp_b0ds = 0x00000030,
695 .grp_b1ds = 0x00000030,
696 .grp_b2ds = 0x00000030,
697 .grp_b3ds = 0x00000030,
698 .grp_b4ds = 0x00000030,
699 .grp_b5ds = 0x00000030,
700 .grp_b6ds = 0x00000030,
701 .grp_b7ds = 0x00000030,
704 const struct mx6_mmdc_calibration mx6_mmcd_calib = {
705 .p0_mpwldectrl0 = 0x001F001F,
706 .p0_mpwldectrl1 = 0x001F001F,
707 .p1_mpwldectrl0 = 0x00440044,
708 .p1_mpwldectrl1 = 0x00440044,
709 .p0_mpdgctrl0 = 0x434B0350,
710 .p0_mpdgctrl1 = 0x034C0359,
711 .p1_mpdgctrl0 = 0x434B0350,
712 .p1_mpdgctrl1 = 0x03650348,
713 .p0_mprddlctl = 0x4436383B,
714 .p1_mprddlctl = 0x39393341,
715 .p0_mpwrdlctl = 0x35373933,
716 .p1_mpwrdlctl = 0x48254A36,
719 static struct mx6_ddr3_cfg mem_ddr = {
732 static void ccgr_init(void)
734 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
736 writel(0x00C03F3F, &ccm->CCGR0);
737 writel(0x0030FC03, &ccm->CCGR1);
738 writel(0x0FFFC000, &ccm->CCGR2);
739 writel(0x3FF00000, &ccm->CCGR3);
740 writel(0x00FFF300, &ccm->CCGR4);
741 writel(0x0F0000C3, &ccm->CCGR5);
742 writel(0x000003FF, &ccm->CCGR6);
745 static void gpr_init(void)
747 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
749 /* enable AXI cache for VDOA/VPU/IPU */
750 writel(0xF00000CF, &iomux->gpr[4]);
751 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
752 writel(0x007F007F, &iomux->gpr[6]);
753 writel(0x007F007F, &iomux->gpr[7]);
757 * This section requires the differentiation between iMX6 Sabre boards, but
758 * for now, it will configure only for the mx6q variant.
760 static void spl_dram_init(void)
762 struct mx6_ddr_sysinfo sysinfo = {
763 /* width of data bus:0=16,1=32,2=64 */
764 .dsize = mem_ddr.width/32,
765 /* config for full 4GB range so that get_mem_size() works */
766 .cs_density = 32, /* 32Gb per CS */
767 /* single chip select */
770 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
771 #ifdef RTT_NOM_120OHM
772 .rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */
774 .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */
776 .walat = 1, /* Write additional latency */
777 .ralat = 5, /* Read additional latency */
778 .mif3_mode = 3, /* Command prediction working mode */
779 .bi_on = 1, /* Bank interleaving enabled */
780 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
781 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
784 mx6dq_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
785 mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
788 void board_init_f(ulong dummy)
790 /* setup AIPS and disable watchdog */
796 /* iomux and setup of i2c */
797 board_early_init_f();
802 /* UART clocks enabled and gd valid - init serial console */
803 preloader_console_init();
805 /* DDR initialization */
809 memset(__bss_start, 0, __bss_end - __bss_start);
811 /* load/boot image from boot device */
812 board_init_r(NULL, 0);
815 void reset_cpu(ulong addr)