board/freescale/mx6sabresd/mx6sabresd.c

   1 /*
   2  * Copyright (C) 2012 Freescale Semiconductor, Inc.
   3  *
   4  * Author: Fabio Estevam <fabio.estevam@freescale.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <asm/arch/clock.h>
  10 #include <asm/arch/imx-regs.h>
  11 #include <asm/arch/iomux.h>
  12 #include <asm/arch/mx6-pins.h>
  13 #include <asm/errno.h>
  14 #include <asm/gpio.h>
  15 #include <asm/imx-common/mxc_i2c.h>
  16 #include <asm/imx-common/iomux-v3.h>
  17 #include <asm/imx-common/boot_mode.h>
  18 #include <asm/imx-common/video.h>
  19 #include <mmc.h>
  20 #include <fsl_esdhc.h>
  21 #include <miiphy.h>
  22 #include <netdev.h>
  23 #include <asm/arch/mxc_hdmi.h>
  24 #include <asm/arch/crm_regs.h>
  25 #include <asm/io.h>
  26 #include <asm/arch/sys_proto.h>
  27 #include <i2c.h>
  28 #include <power/pmic.h>
  29 #include <power/pfuze100_pmic.h>
  30 #include <asm/arch/mx6-ddr.h>
  31
  32 DECLARE_GLOBAL_DATA_PTR;
  33
  34 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  35         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  36         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  37
  38 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  39         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  40         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  41
  42 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  43         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  44
  45 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
  46                       PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  47
  48 #define I2C_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                    \
  49         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  50         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  51
  52 #define I2C_PMIC        1
  53
  54 #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
  55
  56 #define DISP0_PWR_EN    IMX_GPIO_NR(1, 21)
  57
  58 int dram_init(void)
  59 {
  60         gd->ram_size = imx_ddr_size();
  61         return 0;
  62 }
  63
  64 static iomux_v3_cfg_t const uart1_pads[] = {
  65         MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  66         MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  67 };
  68
  69 static iomux_v3_cfg_t const enet_pads[] = {
  70         MX6_PAD_ENET_MDIO__ENET_MDIO            | MUX_PAD_CTRL(ENET_PAD_CTRL),
  71         MX6_PAD_ENET_MDC__ENET_MDC              | MUX_PAD_CTRL(ENET_PAD_CTRL),
  72         MX6_PAD_RGMII_TXC__RGMII_TXC    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  73         MX6_PAD_RGMII_TD0__RGMII_TD0    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  74         MX6_PAD_RGMII_TD1__RGMII_TD1    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  75         MX6_PAD_RGMII_TD2__RGMII_TD2    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  76         MX6_PAD_RGMII_TD3__RGMII_TD3    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  77         MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
  78         MX6_PAD_ENET_REF_CLK__ENET_TX_CLK       | MUX_PAD_CTRL(ENET_PAD_CTRL),
  79         MX6_PAD_RGMII_RXC__RGMII_RXC    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  80         MX6_PAD_RGMII_RD0__RGMII_RD0    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  81         MX6_PAD_RGMII_RD1__RGMII_RD1    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  82         MX6_PAD_RGMII_RD2__RGMII_RD2    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  83         MX6_PAD_RGMII_RD3__RGMII_RD3    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  84         MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
  85         /* AR8031 PHY Reset */
  86         MX6_PAD_ENET_CRS_DV__GPIO1_IO25         | MUX_PAD_CTRL(NO_PAD_CTRL),
  87 };
  88
  89 static void setup_iomux_enet(void)
  90 {
  91         imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
  92
  93         /* Reset AR8031 PHY */
  94         gpio_direction_output(IMX_GPIO_NR(1, 25) , 0);
  95         udelay(500);
  96         gpio_set_value(IMX_GPIO_NR(1, 25), 1);
  97 }
  98
  99 static iomux_v3_cfg_t const usdhc2_pads[] = {
 100         MX6_PAD_SD2_CLK__SD2_CLK        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 101         MX6_PAD_SD2_CMD__SD2_CMD        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 102         MX6_PAD_SD2_DAT0__SD2_DATA0     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 103         MX6_PAD_SD2_DAT1__SD2_DATA1     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 104         MX6_PAD_SD2_DAT2__SD2_DATA2     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 105         MX6_PAD_SD2_DAT3__SD2_DATA3     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 106         MX6_PAD_NANDF_D4__SD2_DATA4     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 107         MX6_PAD_NANDF_D5__SD2_DATA5     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 108         MX6_PAD_NANDF_D6__SD2_DATA6     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 109         MX6_PAD_NANDF_D7__SD2_DATA7     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 110         MX6_PAD_NANDF_D2__GPIO2_IO02    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 111 };
 112
 113 static iomux_v3_cfg_t const usdhc3_pads[] = {
 114         MX6_PAD_SD3_CLK__SD3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 115         MX6_PAD_SD3_CMD__SD3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 116         MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 117         MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 118         MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 119         MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 120         MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 121         MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 122         MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 123         MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 124         MX6_PAD_NANDF_D0__GPIO2_IO00    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 125 };
 126
 127 static iomux_v3_cfg_t const usdhc4_pads[] = {
 128         MX6_PAD_SD4_CLK__SD4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 129         MX6_PAD_SD4_CMD__SD4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 130         MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 131         MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 132         MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 133         MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 134         MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 135         MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 136         MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 137         MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 138 };
 139
 140 static iomux_v3_cfg_t const ecspi1_pads[] = {
 141         MX6_PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
 142         MX6_PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
 143         MX6_PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
 144         MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
 145 };
 146
 147 static iomux_v3_cfg_t const rgb_pads[] = {
 148         MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL),
 149         MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL),
 150         MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(NO_PAD_CTRL),
 151         MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(NO_PAD_CTRL),
 152         MX6_PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(NO_PAD_CTRL),
 153         MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL),
 154         MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL),
 155         MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL),
 156         MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL),
 157         MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL),
 158         MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL),
 159         MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL),
 160         MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL),
 161         MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(NO_PAD_CTRL),
 162         MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(NO_PAD_CTRL),
 163         MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(NO_PAD_CTRL),
 164         MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(NO_PAD_CTRL),
 165         MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(NO_PAD_CTRL),
 166         MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(NO_PAD_CTRL),
 167         MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(NO_PAD_CTRL),
 168         MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(NO_PAD_CTRL),
 169         MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(NO_PAD_CTRL),
 170         MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(NO_PAD_CTRL),
 171         MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 | MUX_PAD_CTRL(NO_PAD_CTRL),
 172         MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 | MUX_PAD_CTRL(NO_PAD_CTRL),
 173         MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 | MUX_PAD_CTRL(NO_PAD_CTRL),
 174         MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 | MUX_PAD_CTRL(NO_PAD_CTRL),
 175         MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 | MUX_PAD_CTRL(NO_PAD_CTRL),
 176         MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 | MUX_PAD_CTRL(NO_PAD_CTRL),
 177         MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
 178 };
 179
 180 static void enable_rgb(struct display_info_t const *dev)
 181 {
 182         imx_iomux_v3_setup_multiple_pads(rgb_pads, ARRAY_SIZE(rgb_pads));
 183         gpio_direction_output(DISP0_PWR_EN, 1);
 184 }
 185
 186 static struct i2c_pads_info i2c_pad_info1 = {
 187         .scl = {
 188                 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
 189                 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
 190                 .gp = IMX_GPIO_NR(4, 12)
 191         },
 192         .sda = {
 193                 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
 194                 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
 195                 .gp = IMX_GPIO_NR(4, 13)
 196         }
 197 };
 198
 199 static void setup_spi(void)
 200 {
 201         imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
 202 }
 203
 204 iomux_v3_cfg_t const pcie_pads[] = {
 205         MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),        /* POWER */
 206         MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),        /* RESET */
 207 };
 208
 209 static void setup_pcie(void)
 210 {
 211         imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
 212 }
 213
 214 iomux_v3_cfg_t const di0_pads[] = {
 215         MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,        /* DISP0_CLK */
 216         MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02,               /* DISP0_HSYNC */
 217         MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03,               /* DISP0_VSYNC */
 218 };
 219
 220 static void setup_iomux_uart(void)
 221 {
 222         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 223 }
 224
 225 #ifdef CONFIG_FSL_ESDHC
 226 struct fsl_esdhc_cfg usdhc_cfg[3] = {
 227         {USDHC2_BASE_ADDR},
 228         {USDHC3_BASE_ADDR},
 229         {USDHC4_BASE_ADDR},
 230 };
 231
 232 #define USDHC2_CD_GPIO  IMX_GPIO_NR(2, 2)
 233 #define USDHC3_CD_GPIO  IMX_GPIO_NR(2, 0)
 234
 235 int board_mmc_getcd(struct mmc *mmc)
 236 {
 237         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 238         int ret = 0;
 239
 240         switch (cfg->esdhc_base) {
 241         case USDHC2_BASE_ADDR:
 242                 ret = !gpio_get_value(USDHC2_CD_GPIO);
 243                 break;
 244         case USDHC3_BASE_ADDR:
 245                 ret = !gpio_get_value(USDHC3_CD_GPIO);
 246                 break;
 247         case USDHC4_BASE_ADDR:
 248                 ret = 1; /* eMMC/uSDHC4 is always present */
 249                 break;
 250         }
 251
 252         return ret;
 253 }
 254
 255 int board_mmc_init(bd_t *bis)
 256 {
 257 #ifndef CONFIG_SPL_BUILD
 258         int ret;
 259         int i;
 260
 261         /*
 262          * According to the board_mmc_init() the following map is done:
 263          * (U-boot device node)    (Physical Port)
 264          * mmc0                    SD2
 265          * mmc1                    SD3
 266          * mmc2                    eMMC
 267          */
 268         for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
 269                 switch (i) {
 270                 case 0:
 271                         imx_iomux_v3_setup_multiple_pads(
 272                                 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
 273                         gpio_direction_input(USDHC2_CD_GPIO);
 274                         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 275                         break;
 276                 case 1:
 277                         imx_iomux_v3_setup_multiple_pads(
 278                                 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 279                         gpio_direction_input(USDHC3_CD_GPIO);
 280                         usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 281                         break;
 282                 case 2:
 283                         imx_iomux_v3_setup_multiple_pads(
 284                                 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
 285                         usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 286                         break;
 287                 default:
 288                         printf("Warning: you configured more USDHC controllers"
 289                                "(%d) then supported by the board (%d)\n",
 290                                i + 1, CONFIG_SYS_FSL_USDHC_NUM);
 291                         return -EINVAL;
 292                 }
 293
 294                 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 295                 if (ret)
 296                         return ret;
 297         }
 298
 299         return 0;
 300 #else
 301         struct src *psrc = (struct src *)SRC_BASE_ADDR;
 302         unsigned reg = readl(&psrc->sbmr1) >> 11;
 303         /*
 304          * Upon reading BOOT_CFG register the following map is done:
 305          * Bit 11 and 12 of BOOT_CFG register can determine the current
 306          * mmc port
 307          * 0x1                  SD1
 308          * 0x2                  SD2
 309          * 0x3                  SD4
 310          */
 311
 312         switch (reg & 0x3) {
 313         case 0x1:
 314                 imx_iomux_v3_setup_multiple_pads(
 315                         usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
 316                 usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
 317                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 318                 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 319                 break;
 320         case 0x2:
 321                 imx_iomux_v3_setup_multiple_pads(
 322                         usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 323                 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
 324                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 325                 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 326                 break;
 327         case 0x3:
 328                 imx_iomux_v3_setup_multiple_pads(
 329                         usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
 330                 usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
 331                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 332                 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 333                 break;
 334         }
 335
 336         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 337 #endif
 338 }
 339 #endif
 340
 341 int mx6_rgmii_rework(struct phy_device *phydev)
 342 {
 343         unsigned short val;
 344
 345         /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
 346         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
 347         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
 348         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
 349
 350         val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
 351         val &= 0xffe3;
 352         val |= 0x18;
 353         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
 354
 355         /* introduce tx clock delay */
 356         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
 357         val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
 358         val |= 0x0100;
 359         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
 360
 361         return 0;
 362 }
 363
 364 int board_phy_config(struct phy_device *phydev)
 365 {
 366         mx6_rgmii_rework(phydev);
 367
 368         if (phydev->drv->config)
 369                 phydev->drv->config(phydev);
 370
 371         return 0;
 372 }
 373
 374 #if defined(CONFIG_VIDEO_IPUV3)
 375 static void disable_lvds(struct display_info_t const *dev)
 376 {
 377         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 378
 379         int reg = readl(&iomux->gpr[2]);
 380
 381         reg &= ~(IOMUXC_GPR2_LVDS_CH0_MODE_MASK |
 382                  IOMUXC_GPR2_LVDS_CH1_MODE_MASK);
 383
 384         writel(reg, &iomux->gpr[2]);
 385 }
 386
 387 static void do_enable_hdmi(struct display_info_t const *dev)
 388 {
 389         disable_lvds(dev);
 390         imx_enable_hdmi_phy();
 391 }
 392
 393 static void enable_lvds(struct display_info_t const *dev)
 394 {
 395         struct iomuxc *iomux = (struct iomuxc *)
 396                                 IOMUXC_BASE_ADDR;
 397         u32 reg = readl(&iomux->gpr[2]);
 398         reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
 399                IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT;
 400         writel(reg, &iomux->gpr[2]);
 401 }
 402
 403 struct display_info_t const displays[] = {{
 404         .bus    = -1,
 405         .addr   = 0,
 406         .pixfmt = IPU_PIX_FMT_RGB666,
 407         .detect = NULL,
 408         .enable = enable_lvds,
 409         .mode   = {
 410                 .name           = "Hannstar-XGA",
 411                 .refresh        = 60,
 412                 .xres           = 1024,
 413                 .yres           = 768,
 414                 .pixclock       = 15385,
 415                 .left_margin    = 220,
 416                 .right_margin   = 40,
 417                 .upper_margin   = 21,
 418                 .lower_margin   = 7,
 419                 .hsync_len      = 60,
 420                 .vsync_len      = 10,
 421                 .sync           = FB_SYNC_EXT,
 422                 .vmode          = FB_VMODE_NONINTERLACED
 423 } }, {
 424         .bus    = -1,
 425         .addr   = 0,
 426         .pixfmt = IPU_PIX_FMT_RGB24,
 427         .detect = detect_hdmi,
 428         .enable = do_enable_hdmi,
 429         .mode   = {
 430                 .name           = "HDMI",
 431                 .refresh        = 60,
 432                 .xres           = 1024,
 433                 .yres           = 768,
 434                 .pixclock       = 15385,
 435                 .left_margin    = 220,
 436                 .right_margin   = 40,
 437                 .upper_margin   = 21,
 438                 .lower_margin   = 7,
 439                 .hsync_len      = 60,
 440                 .vsync_len      = 10,
 441                 .sync           = FB_SYNC_EXT,
 442                 .vmode          = FB_VMODE_NONINTERLACED
 443 } }, {
 444         .bus    = 0,
 445         .addr   = 0,
 446         .pixfmt = IPU_PIX_FMT_RGB24,
 447         .detect = NULL,
 448         .enable = enable_rgb,
 449         .mode   = {
 450                 .name           = "SEIKO-WVGA",
 451                 .refresh        = 60,
 452                 .xres           = 800,
 453                 .yres           = 480,
 454                 .pixclock       = 29850,
 455                 .left_margin    = 89,
 456                 .right_margin   = 164,
 457                 .upper_margin   = 23,
 458                 .lower_margin   = 10,
 459                 .hsync_len      = 10,
 460                 .vsync_len      = 10,
 461                 .sync           = 0,
 462                 .vmode          = FB_VMODE_NONINTERLACED
 463 } } };
 464 size_t display_count = ARRAY_SIZE(displays);
 465
 466 static void setup_display(void)
 467 {
 468         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 469         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 470         int reg;
 471
 472         /* Setup HSYNC, VSYNC, DISP_CLK for debugging purposes */
 473         imx_iomux_v3_setup_multiple_pads(di0_pads, ARRAY_SIZE(di0_pads));
 474
 475         enable_ipu_clock();
 476         imx_setup_hdmi();
 477
 478         /* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */
 479         reg = readl(&mxc_ccm->CCGR3);
 480         reg |=  MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
 481         writel(reg, &mxc_ccm->CCGR3);
 482
 483         /* set LDB0, LDB1 clk select to 011/011 */
 484         reg = readl(&mxc_ccm->cs2cdr);
 485         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 486                  | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 487         reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 488               | (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 489         writel(reg, &mxc_ccm->cs2cdr);
 490
 491         reg = readl(&mxc_ccm->cscmr2);
 492         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
 493         writel(reg, &mxc_ccm->cscmr2);
 494
 495         reg = readl(&mxc_ccm->chsccdr);
 496         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 497                 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 498         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 499                 << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
 500         writel(reg, &mxc_ccm->chsccdr);
 501
 502         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 503              | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW
 504              | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 505              | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 506              | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
 507              | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 508              | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
 509              | IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED
 510              | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0;
 511         writel(reg, &iomux->gpr[2]);
 512
 513         reg = readl(&iomux->gpr[3]);
 514         reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK
 515                         | IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
 516             | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 517                << IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET);
 518         writel(reg, &iomux->gpr[3]);
 519 }
 520 #endif /* CONFIG_VIDEO_IPUV3 */
 521
 522 /*
 523  * Do not overwrite the console
 524  * Use always serial for U-Boot console
 525  */
 526 int overwrite_console(void)
 527 {
 528         return 1;
 529 }
 530
 531 int board_eth_init(bd_t *bis)
 532 {
 533         setup_iomux_enet();
 534         setup_pcie();
 535
 536         return cpu_eth_init(bis);
 537 }
 538
 539 int board_early_init_f(void)
 540 {
 541         setup_iomux_uart();
 542 #if defined(CONFIG_VIDEO_IPUV3)
 543         setup_display();
 544 #endif
 545
 546         return 0;
 547 }
 548
 549 int board_init(void)
 550 {
 551         /* address of boot parameters */
 552         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 553
 554 #ifdef CONFIG_MXC_SPI
 555         setup_spi();
 556 #endif
 557         setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 558
 559         return 0;
 560 }
 561
 562 static int pfuze_init(void)
 563 {
 564         struct pmic *p;
 565         int ret;
 566         unsigned int reg;
 567
 568         ret = power_pfuze100_init(I2C_PMIC);
 569         if (ret)
 570                 return ret;
 571
 572         p = pmic_get("PFUZE100");
 573         ret = pmic_probe(p);
 574         if (ret)
 575                 return ret;
 576
 577         pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
 578         printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
 579
 580         /* Increase VGEN3 from 2.5 to 2.8V */
 581         pmic_reg_read(p, PFUZE100_VGEN3VOL, &reg);
 582         reg &= ~0xf;
 583         reg |= 0xa;
 584         pmic_reg_write(p, PFUZE100_VGEN3VOL, reg);
 585
 586         /* Increase VGEN5 from 2.8 to 3V */
 587         pmic_reg_read(p, PFUZE100_VGEN5VOL, &reg);
 588         reg &= ~0xf;
 589         reg |= 0xc;
 590         pmic_reg_write(p, PFUZE100_VGEN5VOL, reg);
 591
 592         /* Set SW1AB stanby volage to 0.975V */
 593         pmic_reg_read(p, PFUZE100_SW1ABSTBY, &reg);
 594         reg &= ~0x3f;
 595         reg |= 0x1b;
 596         pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
 597
 598         /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
 599         pmic_reg_read(p, PUZE_100_SW1ABCONF, &reg);
 600         reg &= ~0xc0;
 601         reg |= 0x40;
 602         pmic_reg_write(p, PUZE_100_SW1ABCONF, reg);
 603
 604         /* Set SW1C standby voltage to 0.975V */
 605         pmic_reg_read(p, PFUZE100_SW1CSTBY, &reg);
 606         reg &= ~0x3f;
 607         reg |= 0x1b;
 608         pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
 609
 610         /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
 611         pmic_reg_read(p, PFUZE100_SW1CCONF, &reg);
 612         reg &= ~0xc0;
 613         reg |= 0x40;
 614         pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
 615
 616         return 0;
 617 }
 618
 619 #ifdef CONFIG_MXC_SPI
 620 int board_spi_cs_gpio(unsigned bus, unsigned cs)
 621 {
 622         return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1;
 623 }
 624 #endif
 625
 626 #ifdef CONFIG_CMD_BMODE
 627 static const struct boot_mode board_boot_modes[] = {
 628         /* 4 bit bus width */
 629         {"sd2",  MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
 630         {"sd3",  MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 631         /* 8 bit bus width */
 632         {"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
 633         {NULL,   0},
 634 };
 635 #endif
 636
 637 int board_late_init(void)
 638 {
 639 #ifdef CONFIG_CMD_BMODE
 640         add_board_boot_modes(board_boot_modes);
 641 #endif
 642         pfuze_init();
 643
 644         return 0;
 645 }
 646
 647 int checkboard(void)
 648 {
 649         puts("Board: MX6-SabreSD\n");
 650         return 0;
 651 }
 652
 653 #ifdef CONFIG_SPL_BUILD
 654 #include <spl.h>
 655 #include <libfdt.h>
 656
 657 const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
 658         .dram_sdclk_0 =  0x00020030,
 659         .dram_sdclk_1 =  0x00020030,
 660         .dram_cas =  0x00020030,
 661         .dram_ras =  0x00020030,
 662         .dram_reset =  0x00020030,
 663         .dram_sdcke0 =  0x00003000,
 664         .dram_sdcke1 =  0x00003000,
 665         .dram_sdba2 =  0x00000000,
 666         .dram_sdodt0 =  0x00003030,
 667         .dram_sdodt1 =  0x00003030,
 668         .dram_sdqs0 =  0x00000030,
 669         .dram_sdqs1 =  0x00000030,
 670         .dram_sdqs2 =  0x00000030,
 671         .dram_sdqs3 =  0x00000030,
 672         .dram_sdqs4 =  0x00000030,
 673         .dram_sdqs5 =  0x00000030,
 674         .dram_sdqs6 =  0x00000030,
 675         .dram_sdqs7 =  0x00000030,
 676         .dram_dqm0 =  0x00020030,
 677         .dram_dqm1 =  0x00020030,
 678         .dram_dqm2 =  0x00020030,
 679         .dram_dqm3 =  0x00020030,
 680         .dram_dqm4 =  0x00020030,
 681         .dram_dqm5 =  0x00020030,
 682         .dram_dqm6 =  0x00020030,
 683         .dram_dqm7 =  0x00020030,
 684 };
 685
 686 const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
 687         .grp_ddr_type =  0x000C0000,
 688         .grp_ddrmode_ctl =  0x00020000,
 689         .grp_ddrpke =  0x00000000,
 690         .grp_addds =  0x00000030,
 691         .grp_ctlds =  0x00000030,
 692         .grp_ddrmode =  0x00020000,
 693         .grp_b0ds =  0x00000030,
 694         .grp_b1ds =  0x00000030,
 695         .grp_b2ds =  0x00000030,
 696         .grp_b3ds =  0x00000030,
 697         .grp_b4ds =  0x00000030,
 698         .grp_b5ds =  0x00000030,
 699         .grp_b6ds =  0x00000030,
 700         .grp_b7ds =  0x00000030,
 701 };
 702
 703 const struct mx6_mmdc_calibration mx6_mmcd_calib = {
 704         .p0_mpwldectrl0 =  0x001F001F,
 705         .p0_mpwldectrl1 =  0x001F001F,
 706         .p1_mpwldectrl0 =  0x00440044,
 707         .p1_mpwldectrl1 =  0x00440044,
 708         .p0_mpdgctrl0 =  0x434B0350,
 709         .p0_mpdgctrl1 =  0x034C0359,
 710         .p1_mpdgctrl0 =  0x434B0350,
 711         .p1_mpdgctrl1 =  0x03650348,
 712         .p0_mprddlctl =  0x4436383B,
 713         .p1_mprddlctl =  0x39393341,
 714         .p0_mpwrdlctl =  0x35373933,
 715         .p1_mpwrdlctl =  0x48254A36,
 716 };
 717
 718 static struct mx6_ddr3_cfg mem_ddr = {
 719         .mem_speed = 1600,
 720         .density = 4,
 721         .width = 64,
 722         .banks = 8,
 723         .rowaddr = 14,
 724         .coladdr = 10,
 725         .pagesz = 2,
 726         .trcd = 1375,
 727         .trcmin = 4875,
 728         .trasmin = 3500,
 729 };
 730
 731 static void ccgr_init(void)
 732 {
 733         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 734
 735         writel(0x00C03F3F, &ccm->CCGR0);
 736         writel(0x0030FC03, &ccm->CCGR1);
 737         writel(0x0FFFC000, &ccm->CCGR2);
 738         writel(0x3FF00000, &ccm->CCGR3);
 739         writel(0x00FFF300, &ccm->CCGR4);
 740         writel(0x0F0000C3, &ccm->CCGR5);
 741         writel(0x000003FF, &ccm->CCGR6);
 742 }
 743
 744 static void gpr_init(void)
 745 {
 746         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 747
 748         /* enable AXI cache for VDOA/VPU/IPU */
 749         writel(0xF00000CF, &iomux->gpr[4]);
 750         /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
 751         writel(0x007F007F, &iomux->gpr[6]);
 752         writel(0x007F007F, &iomux->gpr[7]);
 753 }
 754
 755 /*
 756  * This section requires the differentiation between iMX6 Sabre boards, but
 757  * for now, it will configure only for the mx6q variant.
 758  */
 759 static void spl_dram_init(void)
 760 {
 761         struct mx6_ddr_sysinfo sysinfo = {
 762                 /* width of data bus:0=16,1=32,2=64 */
 763                 .dsize = mem_ddr.width/32,
 764                 /* config for full 4GB range so that get_mem_size() works */
 765                 .cs_density = 32, /* 32Gb per CS */
 766                 /* single chip select */
 767                 .ncs = 1,
 768                 .cs1_mirror = 0,
 769                 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/,        /* RTT_Wr = RZQ/4 */
 770 #ifdef RTT_NOM_120OHM
 771                 .rtt_nom = 2 /*DDR3_RTT_120_OHM*/,      /* RTT_Nom = RZQ/2 */
 772 #else
 773                 .rtt_nom = 1 /*DDR3_RTT_60_OHM*/,       /* RTT_Nom = RZQ/4 */
 774 #endif
 775                 .walat = 1,     /* Write additional latency */
 776                 .ralat = 5,     /* Read additional latency */
 777                 .mif3_mode = 3, /* Command prediction working mode */
 778                 .bi_on = 1,     /* Bank interleaving enabled */
 779                 .sde_to_rst = 0x10,     /* 14 cycles, 200us (JEDEC default) */
 780                 .rst_to_cke = 0x23,     /* 33 cycles, 500us (JEDEC default) */
 781         };
 782
 783         mx6dq_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
 784         mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
 785 }
 786
 787 void board_init_f(ulong dummy)
 788 {
 789         /* setup AIPS and disable watchdog */
 790         arch_cpu_init();
 791
 792         ccgr_init();
 793         gpr_init();
 794
 795         /* iomux and setup of i2c */
 796         board_early_init_f();
 797
 798         /* setup GP timer */
 799         timer_init();
 800
 801         /* UART clocks enabled and gd valid - init serial console */
 802         preloader_console_init();
 803
 804         /* DDR initialization */
 805         spl_dram_init();
 806
 807         /* Clear the BSS. */
 808         memset(__bss_start, 0, __bss_end - __bss_start);
 809
 810         /* load/boot image from boot device */
 811         board_init_r(NULL, 0);
 812 }
 813
 814 void reset_cpu(ulong addr)
 815 {
 816 }
 817 #endif