2 * Copyright (C) 2012 Freescale Semiconductor, Inc.
4 * Author: Fabio Estevam <fabio.estevam@freescale.com>
6 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/clock.h>
12 #include <asm/arch/imx-regs.h>
13 #include <asm/arch/iomux.h>
14 #include <asm/arch/mx6-pins.h>
15 #include <asm/errno.h>
17 #include <asm/imx-common/iomux-v3.h>
18 #include <asm/imx-common/mxc_i2c.h>
19 #include <asm/imx-common/boot_mode.h>
20 #include <asm/imx-common/spi.h>
22 #include <fsl_esdhc.h>
25 #include <asm/arch/sys_proto.h>
27 #include <asm/arch/mxc_hdmi.h>
28 #include <asm/imx-common/video.h>
29 #include <asm/arch/crm_regs.h>
31 #include <power/pmic.h>
32 #include "../common/pfuze.h"
34 DECLARE_GLOBAL_DATA_PTR;
36 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
37 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
38 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
40 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
41 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
42 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
44 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
45 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
47 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
48 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
49 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
51 #define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
52 #define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
54 #define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
56 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
58 #define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
59 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
60 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
66 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
71 static iomux_v3_cfg_t const uart4_pads[] = {
72 MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
73 MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
76 static iomux_v3_cfg_t const enet_pads[] = {
77 MX6_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
78 MX6_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
79 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
80 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
81 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
82 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
83 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
84 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
85 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
86 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
87 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
88 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
89 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
90 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
91 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
94 /* I2C2 PMIC, iPod, Tuner, Codec, Touch, HDMI EDID, MIPI CSI2 card */
95 static struct i2c_pads_info i2c_pad_info1 = {
97 .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC,
98 .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
99 .gp = IMX_GPIO_NR(2, 30)
102 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
103 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
104 .gp = IMX_GPIO_NR(4, 13)
108 #ifndef CONFIG_SYS_FLASH_CFI
110 * I2C3 MLB, Port Expanders (A, B, C), Video ADC, Light Sensor,
111 * Compass Sensor, Accelerometer, Res Touch
113 static struct i2c_pads_info i2c_pad_info2 = {
115 .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC,
116 .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC,
117 .gp = IMX_GPIO_NR(1, 3)
120 .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
121 .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
122 .gp = IMX_GPIO_NR(3, 18)
127 static iomux_v3_cfg_t const i2c3_pads[] = {
128 MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
131 static iomux_v3_cfg_t const port_exp[] = {
132 MX6_PAD_SD2_DAT0__GPIO1_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
135 /*Define for building port exp gpio, pin starts from 0*/
136 #define PORTEXP_IO_NR(chip, pin) \
139 /*Get the chip addr from a ioexp gpio*/
140 #define PORTEXP_IO_TO_CHIP(gpio_nr) \
143 /*Get the pin number from a ioexp gpio*/
144 #define PORTEXP_IO_TO_PIN(gpio_nr) \
147 static int port_exp_direction_output(unsigned gpio, int value)
152 ret = i2c_probe(PORTEXP_IO_TO_CHIP(gpio));
156 ret = pca953x_set_dir(PORTEXP_IO_TO_CHIP(gpio),
157 (1 << PORTEXP_IO_TO_PIN(gpio)),
158 (PCA953X_DIR_OUT << PORTEXP_IO_TO_PIN(gpio)));
163 ret = pca953x_set_val(PORTEXP_IO_TO_CHIP(gpio),
164 (1 << PORTEXP_IO_TO_PIN(gpio)),
165 (value << PORTEXP_IO_TO_PIN(gpio)));
173 static iomux_v3_cfg_t const eimnor_pads[] = {
174 MX6_PAD_EIM_D16__EIM_DATA16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
175 MX6_PAD_EIM_D17__EIM_DATA17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
176 MX6_PAD_EIM_D18__EIM_DATA18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
177 MX6_PAD_EIM_D19__EIM_DATA19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
178 MX6_PAD_EIM_D20__EIM_DATA20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
179 MX6_PAD_EIM_D21__EIM_DATA21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
180 MX6_PAD_EIM_D22__EIM_DATA22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
181 MX6_PAD_EIM_D23__EIM_DATA23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
182 MX6_PAD_EIM_D24__EIM_DATA24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
183 MX6_PAD_EIM_D25__EIM_DATA25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
184 MX6_PAD_EIM_D26__EIM_DATA26 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
185 MX6_PAD_EIM_D27__EIM_DATA27 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
186 MX6_PAD_EIM_D28__EIM_DATA28 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
187 MX6_PAD_EIM_D29__EIM_DATA29 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
188 MX6_PAD_EIM_D30__EIM_DATA30 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
189 MX6_PAD_EIM_D31__EIM_DATA31 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
190 MX6_PAD_EIM_DA0__EIM_AD00 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
191 MX6_PAD_EIM_DA1__EIM_AD01 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
192 MX6_PAD_EIM_DA2__EIM_AD02 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
193 MX6_PAD_EIM_DA3__EIM_AD03 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
194 MX6_PAD_EIM_DA4__EIM_AD04 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
195 MX6_PAD_EIM_DA5__EIM_AD05 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
196 MX6_PAD_EIM_DA6__EIM_AD06 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
197 MX6_PAD_EIM_DA7__EIM_AD07 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
198 MX6_PAD_EIM_DA8__EIM_AD08 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
199 MX6_PAD_EIM_DA9__EIM_AD09 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
200 MX6_PAD_EIM_DA10__EIM_AD10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
201 MX6_PAD_EIM_DA11__EIM_AD11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL) ,
202 MX6_PAD_EIM_DA12__EIM_AD12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
203 MX6_PAD_EIM_DA13__EIM_AD13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
204 MX6_PAD_EIM_DA14__EIM_AD14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
205 MX6_PAD_EIM_DA15__EIM_AD15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
206 MX6_PAD_EIM_A16__EIM_ADDR16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
207 MX6_PAD_EIM_A17__EIM_ADDR17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
208 MX6_PAD_EIM_A18__EIM_ADDR18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
209 MX6_PAD_EIM_A19__EIM_ADDR19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
210 MX6_PAD_EIM_A20__EIM_ADDR20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
211 MX6_PAD_EIM_A21__EIM_ADDR21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
212 MX6_PAD_EIM_A22__EIM_ADDR22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
213 MX6_PAD_EIM_A23__EIM_ADDR23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
214 MX6_PAD_EIM_OE__EIM_OE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
215 MX6_PAD_EIM_RW__EIM_RW | MUX_PAD_CTRL(NO_PAD_CTRL),
216 MX6_PAD_EIM_CS0__EIM_CS0_B | MUX_PAD_CTRL(NO_PAD_CTRL),
219 static void eimnor_cs_setup(void)
221 struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
223 writel(0x00020181, &weim_regs->cs0gcr1);
224 writel(0x00000001, &weim_regs->cs0gcr2);
225 writel(0x0a020000, &weim_regs->cs0rcr1);
226 writel(0x0000c000, &weim_regs->cs0rcr2);
227 writel(0x0804a240, &weim_regs->cs0wcr1);
228 writel(0x00000120, &weim_regs->wcr);
230 set_chipselect_size(CS0_128);
233 static void setup_iomux_eimnor(void)
235 imx_iomux_v3_setup_multiple_pads(eimnor_pads, ARRAY_SIZE(eimnor_pads));
237 gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
242 static void setup_iomux_enet(void)
244 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
247 static iomux_v3_cfg_t const usdhc3_pads[] = {
248 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
249 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
250 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
251 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
252 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
253 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
254 MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
255 MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
256 MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
257 MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
258 MX6_PAD_GPIO_18__SD3_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
259 MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
262 static void setup_iomux_uart(void)
264 imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
267 #ifdef CONFIG_FSL_ESDHC
268 static struct fsl_esdhc_cfg usdhc_cfg[1] = {
272 int board_mmc_getcd(struct mmc *mmc)
274 gpio_direction_input(IMX_GPIO_NR(6, 15));
275 return !gpio_get_value(IMX_GPIO_NR(6, 15));
278 int board_mmc_init(bd_t *bis)
280 imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
282 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
283 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
287 #ifdef CONFIG_NAND_MXS
288 static iomux_v3_cfg_t gpmi_pads[] = {
289 MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
290 MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
291 MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
292 MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0),
293 MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
294 MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
295 MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
296 MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
297 MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
298 MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
299 MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
300 MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
301 MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
302 MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
303 MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
304 MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL1),
307 static void setup_gpmi_nand(void)
309 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
311 /* config gpmi nand iomux */
312 imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
314 /* gate ENFC_CLK_ROOT clock first,before clk source switch */
315 clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
316 clrbits_le32(&mxc_ccm->CCGR4,
317 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
319 /* config gpmi and bch clock to 100 MHz */
320 clrsetbits_le32(&mxc_ccm->cs2cdr,
321 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
322 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
323 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
324 MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
325 MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
326 MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
328 /* enable ENFC_CLK_ROOT clock */
329 setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
331 /* enable gpmi and bch clock gating */
332 setbits_le32(&mxc_ccm->CCGR4,
333 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
334 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
335 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
336 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
337 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
339 /* enable apbh clock gating */
340 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
344 int mx6_rgmii_rework(struct phy_device *phydev)
348 /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
349 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
350 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
351 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
353 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
356 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
358 /* introduce tx clock delay */
359 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
360 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
362 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
367 int board_phy_config(struct phy_device *phydev)
369 mx6_rgmii_rework(phydev);
371 if (phydev->drv->config)
372 phydev->drv->config(phydev);
377 int board_eth_init(bd_t *bis)
381 return cpu_eth_init(bis);
384 #define BOARD_REV_B 0x200
385 #define BOARD_REV_A 0x100
387 static int mx6sabre_rev(void)
390 * Get Board ID information from OCOTP_GP1[15:8]
391 * i.MX6Q ARD RevA: 0x01
392 * i.MX6Q ARD RevB: 0x02
394 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
395 struct fuse_bank *bank = &ocotp->bank[4];
396 struct fuse_bank4_regs *fuse =
397 (struct fuse_bank4_regs *)bank->fuse_regs;
398 int reg = readl(&fuse->gp1);
401 switch (reg >> 8 & 0x0F) {
414 u32 get_board_rev(void)
416 int rev = mx6sabre_rev();
418 return (get_cpu_rev() & ~(0xF << 8)) | rev;
421 #if defined(CONFIG_VIDEO_IPUV3)
422 static void do_enable_hdmi(struct display_info_t const *dev)
424 imx_enable_hdmi_phy();
427 struct display_info_t const displays[] = {{
430 .pixfmt = IPU_PIX_FMT_RGB24,
431 .detect = detect_hdmi,
432 .enable = do_enable_hdmi,
446 .vmode = FB_VMODE_NONINTERLACED,
448 size_t display_count = ARRAY_SIZE(displays);
450 static void setup_display(void)
452 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
458 reg = readl(&mxc_ccm->chsccdr);
459 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
460 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
461 writel(reg, &mxc_ccm->chsccdr);
463 #endif /* CONFIG_VIDEO_IPUV3 */
466 * Do not overwrite the console
467 * Use always serial for U-Boot console
469 int overwrite_console(void)
474 int board_early_init_f(void)
477 #ifdef CONFIG_VIDEO_IPUV3
481 #ifdef CONFIG_NAND_MXS
490 /* address of boot parameters */
491 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
493 /* I2C 2 and 3 setup - I2C 3 hw mux with EIM */
494 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
496 gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
497 imx_iomux_v3_setup_multiple_pads(i2c3_pads, ARRAY_SIZE(i2c3_pads));
498 #ifndef CONFIG_SYS_FLASH_CFI
499 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
501 gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
502 imx_iomux_v3_setup_multiple_pads(port_exp, ARRAY_SIZE(port_exp));
504 setup_iomux_eimnor();
508 #ifdef CONFIG_MXC_SPI
509 int board_spi_cs_gpio(unsigned bus, unsigned cs)
511 return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1;
515 int power_init_board(void)
519 p = pfuze_common_init(I2C_PMIC);
526 #ifdef CONFIG_CMD_BMODE
527 static const struct boot_mode board_boot_modes[] = {
528 /* 4 bit bus width */
529 {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
534 int board_late_init(void)
536 #ifdef CONFIG_CMD_BMODE
537 add_board_boot_modes(board_boot_modes);
545 int rev = mx6sabre_rev();
558 printf("Board: MX6Q-Sabreauto rev%s\n", revname);
563 #ifdef CONFIG_USB_EHCI_MX6
564 #define USB_HOST1_PWR PORTEXP_IO_NR(0x32, 7)
565 #define USB_OTG_PWR PORTEXP_IO_NR(0x34, 1)
567 iomux_v3_cfg_t const usb_otg_pads[] = {
568 MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
571 int board_ehci_hcd_init(int port)
575 imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
576 ARRAY_SIZE(usb_otg_pads));
579 * Set daisy chain for otg_pin_id on 6q.
580 * For 6dl, this bit is reserved.
582 imx_iomux_set_gpr_register(1, 13, 1, 0);
587 printf("MXC USB port %d not yet supported\n", port);
593 int board_ehci_power(int port, int on)
598 port_exp_direction_output(USB_OTG_PWR, 1);
600 port_exp_direction_output(USB_OTG_PWR, 0);
604 port_exp_direction_output(USB_HOST1_PWR, 1);
606 port_exp_direction_output(USB_HOST1_PWR, 0);
609 printf("MXC USB port %d not yet supported\n", port);