2 * Copyright (C) 2012 Freescale Semiconductor, Inc.
4 * Author: Fabio Estevam <fabio.estevam@freescale.com>
6 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/clock.h>
12 #include <asm/arch/imx-regs.h>
13 #include <asm/arch/iomux.h>
14 #include <asm/arch/mx6-pins.h>
15 #include <asm/errno.h>
17 #include <asm/imx-common/iomux-v3.h>
18 #include <asm/imx-common/mxc_i2c.h>
19 #include <asm/imx-common/boot_mode.h>
20 #include <asm/imx-common/spi.h>
22 #include <fsl_esdhc.h>
25 #include <asm/arch/sys_proto.h>
27 #include <asm/arch/mxc_hdmi.h>
28 #include <asm/imx-common/video.h>
29 #include <asm/arch/crm_regs.h>
32 DECLARE_GLOBAL_DATA_PTR;
34 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
35 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
36 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
38 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
39 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
40 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
42 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
43 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
45 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
46 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
47 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
49 #define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
50 #define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
52 #define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
54 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
58 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
63 static iomux_v3_cfg_t const uart4_pads[] = {
64 MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
65 MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
68 static iomux_v3_cfg_t const enet_pads[] = {
69 MX6_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
70 MX6_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
71 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
72 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
73 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
74 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
75 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
76 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
77 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
78 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
79 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
80 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
81 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
82 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
83 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
86 /* I2C2 PMIC, iPod, Tuner, Codec, Touch, HDMI EDID, MIPI CSI2 card */
87 static struct i2c_pads_info i2c_pad_info1 = {
89 .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC,
90 .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
91 .gp = IMX_GPIO_NR(2, 30)
94 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
95 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
96 .gp = IMX_GPIO_NR(4, 13)
101 * I2C3 MLB, Port Expanders (A, B, C), Video ADC, Light Sensor,
102 * Compass Sensor, Accelerometer, Res Touch
104 static struct i2c_pads_info i2c_pad_info2 = {
106 .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC,
107 .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC,
108 .gp = IMX_GPIO_NR(1, 3)
111 .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
112 .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
113 .gp = IMX_GPIO_NR(3, 18)
117 static iomux_v3_cfg_t const i2c3_pads[] = {
118 MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
121 static iomux_v3_cfg_t const port_exp[] = {
122 MX6_PAD_SD2_DAT0__GPIO1_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
125 /*Define for building port exp gpio, pin starts from 0*/
126 #define PORTEXP_IO_NR(chip, pin) \
129 /*Get the chip addr from a ioexp gpio*/
130 #define PORTEXP_IO_TO_CHIP(gpio_nr) \
133 /*Get the pin number from a ioexp gpio*/
134 #define PORTEXP_IO_TO_PIN(gpio_nr) \
137 static int port_exp_direction_output(unsigned gpio, int value)
142 ret = i2c_probe(PORTEXP_IO_TO_CHIP(gpio));
146 ret = pca953x_set_dir(PORTEXP_IO_TO_CHIP(gpio),
147 (1 << PORTEXP_IO_TO_PIN(gpio)),
148 (PCA953X_DIR_OUT << PORTEXP_IO_TO_PIN(gpio)));
153 ret = pca953x_set_val(PORTEXP_IO_TO_CHIP(gpio),
154 (1 << PORTEXP_IO_TO_PIN(gpio)),
155 (value << PORTEXP_IO_TO_PIN(gpio)));
163 static void setup_iomux_enet(void)
165 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
168 static iomux_v3_cfg_t const usdhc3_pads[] = {
169 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
170 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
171 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
172 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
173 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
174 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
175 MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
176 MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
177 MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
178 MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
179 MX6_PAD_GPIO_18__SD3_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
180 MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
183 static void setup_iomux_uart(void)
185 imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
188 #ifdef CONFIG_FSL_ESDHC
189 static struct fsl_esdhc_cfg usdhc_cfg[1] = {
193 int board_mmc_getcd(struct mmc *mmc)
195 gpio_direction_input(IMX_GPIO_NR(6, 15));
196 return !gpio_get_value(IMX_GPIO_NR(6, 15));
199 int board_mmc_init(bd_t *bis)
201 imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
203 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
204 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
208 #ifdef CONFIG_NAND_MXS
209 static iomux_v3_cfg_t gpmi_pads[] = {
210 MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
211 MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
212 MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
213 MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0),
214 MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
215 MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
216 MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
217 MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
218 MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
219 MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
220 MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
221 MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
222 MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
223 MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
224 MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
225 MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL1),
228 static void setup_gpmi_nand(void)
230 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
232 /* config gpmi nand iomux */
233 imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
235 /* gate ENFC_CLK_ROOT clock first,before clk source switch */
236 clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
237 clrbits_le32(&mxc_ccm->CCGR4,
238 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
240 /* config gpmi and bch clock to 100 MHz */
241 clrsetbits_le32(&mxc_ccm->cs2cdr,
242 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
243 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
244 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
245 MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
246 MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
247 MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
249 /* enable ENFC_CLK_ROOT clock */
250 setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
252 /* enable gpmi and bch clock gating */
253 setbits_le32(&mxc_ccm->CCGR4,
254 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
255 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
256 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
257 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
258 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
260 /* enable apbh clock gating */
261 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
265 int mx6_rgmii_rework(struct phy_device *phydev)
269 /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
270 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
271 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
272 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
274 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
277 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
279 /* introduce tx clock delay */
280 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
281 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
283 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
288 int board_phy_config(struct phy_device *phydev)
290 mx6_rgmii_rework(phydev);
292 if (phydev->drv->config)
293 phydev->drv->config(phydev);
298 int board_eth_init(bd_t *bis)
302 return cpu_eth_init(bis);
305 #define BOARD_REV_B 0x200
306 #define BOARD_REV_A 0x100
308 static int mx6sabre_rev(void)
311 * Get Board ID information from OCOTP_GP1[15:8]
312 * i.MX6Q ARD RevA: 0x01
313 * i.MX6Q ARD RevB: 0x02
315 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
316 struct fuse_bank *bank = &ocotp->bank[4];
317 struct fuse_bank4_regs *fuse =
318 (struct fuse_bank4_regs *)bank->fuse_regs;
319 int reg = readl(&fuse->gp1);
322 switch (reg >> 8 & 0x0F) {
335 u32 get_board_rev(void)
337 int rev = mx6sabre_rev();
339 return (get_cpu_rev() & ~(0xF << 8)) | rev;
342 #if defined(CONFIG_VIDEO_IPUV3)
343 static void do_enable_hdmi(struct display_info_t const *dev)
345 imx_enable_hdmi_phy();
348 struct display_info_t const displays[] = {{
351 .pixfmt = IPU_PIX_FMT_RGB24,
352 .detect = detect_hdmi,
353 .enable = do_enable_hdmi,
367 .vmode = FB_VMODE_NONINTERLACED,
369 size_t display_count = ARRAY_SIZE(displays);
371 static void setup_display(void)
373 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
379 reg = readl(&mxc_ccm->chsccdr);
380 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
381 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
382 writel(reg, &mxc_ccm->chsccdr);
384 #endif /* CONFIG_VIDEO_IPUV3 */
387 * Do not overwrite the console
388 * Use always serial for U-Boot console
390 int overwrite_console(void)
395 int board_early_init_f(void)
398 #ifdef CONFIG_VIDEO_IPUV3
402 #ifdef CONFIG_NAND_MXS
410 /* address of boot parameters */
411 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
413 /* I2C 2 and 3 setup - I2C 3 hw mux with EIM */
414 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
416 gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
417 imx_iomux_v3_setup_multiple_pads(i2c3_pads, ARRAY_SIZE(i2c3_pads));
418 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
420 gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
421 imx_iomux_v3_setup_multiple_pads(port_exp, ARRAY_SIZE(port_exp));
426 #ifdef CONFIG_MXC_SPI
427 int board_spi_cs_gpio(unsigned bus, unsigned cs)
429 return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1;
433 #ifdef CONFIG_CMD_BMODE
434 static const struct boot_mode board_boot_modes[] = {
435 /* 4 bit bus width */
436 {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
441 int board_late_init(void)
443 #ifdef CONFIG_CMD_BMODE
444 add_board_boot_modes(board_boot_modes);
452 int rev = mx6sabre_rev();
465 printf("Board: MX6Q-Sabreauto rev%s\n", revname);
470 #ifdef CONFIG_USB_EHCI_MX6
471 #define USB_HOST1_PWR PORTEXP_IO_NR(0x32, 7)
472 #define USB_OTG_PWR PORTEXP_IO_NR(0x34, 1)
474 iomux_v3_cfg_t const usb_otg_pads[] = {
475 MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
478 int board_ehci_hcd_init(int port)
482 imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
483 ARRAY_SIZE(usb_otg_pads));
486 * Set daisy chain for otg_pin_id on 6q.
487 * For 6dl, this bit is reserved.
489 imx_iomux_set_gpr_register(1, 13, 1, 0);
494 printf("MXC USB port %d not yet supported\n", port);
500 int board_ehci_power(int port, int on)
505 port_exp_direction_output(USB_OTG_PWR, 1);
507 port_exp_direction_output(USB_OTG_PWR, 0);
511 port_exp_direction_output(USB_HOST1_PWR, 1);
513 port_exp_direction_output(USB_HOST1_PWR, 0);
516 printf("MXC USB port %d not yet supported\n", port);