2 * Copyright (C) 2012 Freescale Semiconductor, Inc.
4 * Author: Fabio Estevam <fabio.estevam@freescale.com>
6 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/clock.h>
12 #include <asm/arch/imx-regs.h>
13 #include <asm/arch/iomux.h>
14 #include <asm/arch/mx6-pins.h>
15 #include <asm/errno.h>
17 #include <asm/imx-common/iomux-v3.h>
18 #include <asm/imx-common/mxc_i2c.h>
19 #include <asm/imx-common/boot_mode.h>
20 #include <asm/imx-common/spi.h>
22 #include <fsl_esdhc.h>
25 #include <asm/arch/sys_proto.h>
27 #include <asm/arch/mxc_hdmi.h>
28 #include <asm/imx-common/video.h>
29 #include <asm/arch/crm_regs.h>
31 #include <power/pmic.h>
32 #include <power/pfuze100_pmic.h>
33 #include "../common/pfuze.h"
35 DECLARE_GLOBAL_DATA_PTR;
37 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
38 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
39 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
41 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
42 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
43 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
45 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
46 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
48 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
49 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
50 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
52 #define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
53 #define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
55 #define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
57 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
59 #define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
60 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
61 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
67 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
72 static iomux_v3_cfg_t const uart4_pads[] = {
73 MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
74 MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
77 static iomux_v3_cfg_t const enet_pads[] = {
78 MX6_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
79 MX6_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
80 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
81 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
82 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
83 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
84 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
85 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
86 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
87 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
88 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
89 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
90 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
91 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
92 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
95 /* I2C2 PMIC, iPod, Tuner, Codec, Touch, HDMI EDID, MIPI CSI2 card */
96 static struct i2c_pads_info i2c_pad_info1 = {
98 .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC,
99 .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
100 .gp = IMX_GPIO_NR(2, 30)
103 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
104 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
105 .gp = IMX_GPIO_NR(4, 13)
109 #ifndef CONFIG_SYS_FLASH_CFI
111 * I2C3 MLB, Port Expanders (A, B, C), Video ADC, Light Sensor,
112 * Compass Sensor, Accelerometer, Res Touch
114 static struct i2c_pads_info i2c_pad_info2 = {
116 .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC,
117 .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC,
118 .gp = IMX_GPIO_NR(1, 3)
121 .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
122 .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
123 .gp = IMX_GPIO_NR(3, 18)
128 static iomux_v3_cfg_t const i2c3_pads[] = {
129 MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
132 static iomux_v3_cfg_t const port_exp[] = {
133 MX6_PAD_SD2_DAT0__GPIO1_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
136 /*Define for building port exp gpio, pin starts from 0*/
137 #define PORTEXP_IO_NR(chip, pin) \
140 /*Get the chip addr from a ioexp gpio*/
141 #define PORTEXP_IO_TO_CHIP(gpio_nr) \
144 /*Get the pin number from a ioexp gpio*/
145 #define PORTEXP_IO_TO_PIN(gpio_nr) \
148 static int port_exp_direction_output(unsigned gpio, int value)
153 ret = i2c_probe(PORTEXP_IO_TO_CHIP(gpio));
157 ret = pca953x_set_dir(PORTEXP_IO_TO_CHIP(gpio),
158 (1 << PORTEXP_IO_TO_PIN(gpio)),
159 (PCA953X_DIR_OUT << PORTEXP_IO_TO_PIN(gpio)));
164 ret = pca953x_set_val(PORTEXP_IO_TO_CHIP(gpio),
165 (1 << PORTEXP_IO_TO_PIN(gpio)),
166 (value << PORTEXP_IO_TO_PIN(gpio)));
174 static iomux_v3_cfg_t const eimnor_pads[] = {
175 MX6_PAD_EIM_D16__EIM_DATA16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
176 MX6_PAD_EIM_D17__EIM_DATA17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
177 MX6_PAD_EIM_D18__EIM_DATA18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
178 MX6_PAD_EIM_D19__EIM_DATA19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
179 MX6_PAD_EIM_D20__EIM_DATA20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
180 MX6_PAD_EIM_D21__EIM_DATA21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
181 MX6_PAD_EIM_D22__EIM_DATA22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
182 MX6_PAD_EIM_D23__EIM_DATA23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
183 MX6_PAD_EIM_D24__EIM_DATA24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
184 MX6_PAD_EIM_D25__EIM_DATA25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
185 MX6_PAD_EIM_D26__EIM_DATA26 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
186 MX6_PAD_EIM_D27__EIM_DATA27 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
187 MX6_PAD_EIM_D28__EIM_DATA28 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
188 MX6_PAD_EIM_D29__EIM_DATA29 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
189 MX6_PAD_EIM_D30__EIM_DATA30 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
190 MX6_PAD_EIM_D31__EIM_DATA31 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
191 MX6_PAD_EIM_DA0__EIM_AD00 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
192 MX6_PAD_EIM_DA1__EIM_AD01 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
193 MX6_PAD_EIM_DA2__EIM_AD02 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
194 MX6_PAD_EIM_DA3__EIM_AD03 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
195 MX6_PAD_EIM_DA4__EIM_AD04 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
196 MX6_PAD_EIM_DA5__EIM_AD05 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
197 MX6_PAD_EIM_DA6__EIM_AD06 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
198 MX6_PAD_EIM_DA7__EIM_AD07 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
199 MX6_PAD_EIM_DA8__EIM_AD08 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
200 MX6_PAD_EIM_DA9__EIM_AD09 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
201 MX6_PAD_EIM_DA10__EIM_AD10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
202 MX6_PAD_EIM_DA11__EIM_AD11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL) ,
203 MX6_PAD_EIM_DA12__EIM_AD12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
204 MX6_PAD_EIM_DA13__EIM_AD13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
205 MX6_PAD_EIM_DA14__EIM_AD14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
206 MX6_PAD_EIM_DA15__EIM_AD15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
207 MX6_PAD_EIM_A16__EIM_ADDR16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
208 MX6_PAD_EIM_A17__EIM_ADDR17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
209 MX6_PAD_EIM_A18__EIM_ADDR18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
210 MX6_PAD_EIM_A19__EIM_ADDR19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
211 MX6_PAD_EIM_A20__EIM_ADDR20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
212 MX6_PAD_EIM_A21__EIM_ADDR21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
213 MX6_PAD_EIM_A22__EIM_ADDR22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
214 MX6_PAD_EIM_A23__EIM_ADDR23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
215 MX6_PAD_EIM_OE__EIM_OE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
216 MX6_PAD_EIM_RW__EIM_RW | MUX_PAD_CTRL(NO_PAD_CTRL),
217 MX6_PAD_EIM_CS0__EIM_CS0_B | MUX_PAD_CTRL(NO_PAD_CTRL),
220 static void eimnor_cs_setup(void)
222 struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
224 writel(0x00020181, &weim_regs->cs0gcr1);
225 writel(0x00000001, &weim_regs->cs0gcr2);
226 writel(0x0a020000, &weim_regs->cs0rcr1);
227 writel(0x0000c000, &weim_regs->cs0rcr2);
228 writel(0x0804a240, &weim_regs->cs0wcr1);
229 writel(0x00000120, &weim_regs->wcr);
231 set_chipselect_size(CS0_128);
234 static void setup_iomux_eimnor(void)
236 imx_iomux_v3_setup_multiple_pads(eimnor_pads, ARRAY_SIZE(eimnor_pads));
238 gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
243 static void setup_iomux_enet(void)
245 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
248 static iomux_v3_cfg_t const usdhc3_pads[] = {
249 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
250 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
251 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
252 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
253 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
254 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
255 MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
256 MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
257 MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
258 MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
259 MX6_PAD_GPIO_18__SD3_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
260 MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
263 static void setup_iomux_uart(void)
265 imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
268 #ifdef CONFIG_FSL_ESDHC
269 static struct fsl_esdhc_cfg usdhc_cfg[1] = {
273 int board_mmc_getcd(struct mmc *mmc)
275 gpio_direction_input(IMX_GPIO_NR(6, 15));
276 return !gpio_get_value(IMX_GPIO_NR(6, 15));
279 int board_mmc_init(bd_t *bis)
281 imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
283 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
284 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
288 #ifdef CONFIG_NAND_MXS
289 static iomux_v3_cfg_t gpmi_pads[] = {
290 MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
291 MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
292 MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
293 MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0),
294 MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
295 MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
296 MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
297 MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
298 MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
299 MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
300 MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
301 MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
302 MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
303 MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
304 MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
305 MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL1),
308 static void setup_gpmi_nand(void)
310 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
312 /* config gpmi nand iomux */
313 imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
315 setup_gpmi_io_clk((MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
316 MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
317 MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)));
319 /* enable apbh clock gating */
320 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
324 int mx6_rgmii_rework(struct phy_device *phydev)
328 /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
329 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
330 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
331 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
333 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
336 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
338 /* introduce tx clock delay */
339 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
340 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
342 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
347 int board_phy_config(struct phy_device *phydev)
349 mx6_rgmii_rework(phydev);
351 if (phydev->drv->config)
352 phydev->drv->config(phydev);
357 int board_eth_init(bd_t *bis)
361 return cpu_eth_init(bis);
364 #define BOARD_REV_B 0x200
365 #define BOARD_REV_A 0x100
367 static int mx6sabre_rev(void)
370 * Get Board ID information from OCOTP_GP1[15:8]
371 * i.MX6Q ARD RevA: 0x01
372 * i.MX6Q ARD RevB: 0x02
374 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
375 struct fuse_bank *bank = &ocotp->bank[4];
376 struct fuse_bank4_regs *fuse =
377 (struct fuse_bank4_regs *)bank->fuse_regs;
378 int reg = readl(&fuse->gp1);
381 switch (reg >> 8 & 0x0F) {
394 u32 get_board_rev(void)
396 int rev = mx6sabre_rev();
398 return (get_cpu_rev() & ~(0xF << 8)) | rev;
401 #if defined(CONFIG_VIDEO_IPUV3)
402 static void do_enable_hdmi(struct display_info_t const *dev)
404 imx_enable_hdmi_phy();
407 struct display_info_t const displays[] = {{
410 .pixfmt = IPU_PIX_FMT_RGB24,
411 .detect = detect_hdmi,
412 .enable = do_enable_hdmi,
426 .vmode = FB_VMODE_NONINTERLACED,
428 size_t display_count = ARRAY_SIZE(displays);
430 static void setup_display(void)
432 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
438 reg = readl(&mxc_ccm->chsccdr);
439 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
440 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
441 writel(reg, &mxc_ccm->chsccdr);
443 #endif /* CONFIG_VIDEO_IPUV3 */
446 * Do not overwrite the console
447 * Use always serial for U-Boot console
449 int overwrite_console(void)
454 int board_early_init_f(void)
457 #ifdef CONFIG_VIDEO_IPUV3
461 #ifdef CONFIG_NAND_MXS
470 /* address of boot parameters */
471 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
473 /* I2C 2 and 3 setup - I2C 3 hw mux with EIM */
474 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
476 gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
477 imx_iomux_v3_setup_multiple_pads(i2c3_pads, ARRAY_SIZE(i2c3_pads));
478 #ifndef CONFIG_SYS_FLASH_CFI
479 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
481 gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
482 imx_iomux_v3_setup_multiple_pads(port_exp, ARRAY_SIZE(port_exp));
484 setup_iomux_eimnor();
488 #ifdef CONFIG_MXC_SPI
489 int board_spi_cs_gpio(unsigned bus, unsigned cs)
491 return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1;
495 int power_init_board(void)
500 p = pfuze_common_init(I2C_PMIC);
504 ret = pfuze_mode_init(p, APS_PFM);
511 #ifdef CONFIG_CMD_BMODE
512 static const struct boot_mode board_boot_modes[] = {
513 /* 4 bit bus width */
514 {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
519 int board_late_init(void)
521 #ifdef CONFIG_CMD_BMODE
522 add_board_boot_modes(board_boot_modes);
530 int rev = mx6sabre_rev();
543 printf("Board: MX6Q-Sabreauto rev%s\n", revname);
548 #ifdef CONFIG_USB_EHCI_MX6
549 #define USB_HOST1_PWR PORTEXP_IO_NR(0x32, 7)
550 #define USB_OTG_PWR PORTEXP_IO_NR(0x34, 1)
552 iomux_v3_cfg_t const usb_otg_pads[] = {
553 MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
556 int board_ehci_hcd_init(int port)
560 imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
561 ARRAY_SIZE(usb_otg_pads));
564 * Set daisy chain for otg_pin_id on 6q.
565 * For 6dl, this bit is reserved.
567 imx_iomux_set_gpr_register(1, 13, 1, 0);
572 printf("MXC USB port %d not yet supported\n", port);
578 int board_ehci_power(int port, int on)
583 port_exp_direction_output(USB_OTG_PWR, 1);
585 port_exp_direction_output(USB_OTG_PWR, 0);
589 port_exp_direction_output(USB_HOST1_PWR, 1);
591 port_exp_direction_output(USB_HOST1_PWR, 0);
594 printf("MXC USB port %d not yet supported\n", port);