2 * Copyright (C) 2012 Freescale Semiconductor, Inc.
4 * Author: Fabio Estevam <fabio.estevam@freescale.com>
6 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/clock.h>
12 #include <asm/arch/imx-regs.h>
13 #include <asm/arch/iomux.h>
14 #include <asm/arch/mx6-pins.h>
15 #include <asm/errno.h>
17 #include <asm/imx-common/iomux-v3.h>
18 #include <asm/imx-common/mxc_i2c.h>
19 #include <asm/imx-common/boot_mode.h>
20 #include <asm/imx-common/spi.h>
22 #include <fsl_esdhc.h>
25 #include <asm/arch/sys_proto.h>
27 #include <asm/arch/mxc_hdmi.h>
28 #include <asm/imx-common/video.h>
29 #include <asm/arch/crm_regs.h>
31 DECLARE_GLOBAL_DATA_PTR;
33 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
34 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
35 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
37 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
38 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
39 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
41 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
42 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
44 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
45 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
46 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
48 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
52 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
57 static iomux_v3_cfg_t const uart4_pads[] = {
58 MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
59 MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
62 static iomux_v3_cfg_t const enet_pads[] = {
63 MX6_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
64 MX6_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
65 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
66 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
67 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
68 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
69 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
70 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
71 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
72 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
73 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
74 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
75 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
76 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
77 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
80 /* I2C2 PMIC, iPod, Tuner, Codec, Touch, HDMI EDID, MIPI CSI2 card */
81 static struct i2c_pads_info i2c_pad_info1 = {
83 .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC,
84 .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
85 .gp = IMX_GPIO_NR(2, 30)
88 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
89 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
90 .gp = IMX_GPIO_NR(4, 13)
95 * I2C3 MLB, Port Expanders (A, B, C), Video ADC, Light Sensor,
96 * Compass Sensor, Accelerometer, Res Touch
98 static struct i2c_pads_info i2c_pad_info2 = {
100 .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC,
101 .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC,
102 .gp = IMX_GPIO_NR(1, 3)
105 .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
106 .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
107 .gp = IMX_GPIO_NR(3, 18)
111 static iomux_v3_cfg_t const i2c3_pads[] = {
112 MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
115 static iomux_v3_cfg_t const port_exp[] = {
116 MX6_PAD_SD2_DAT0__GPIO1_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
119 static void setup_iomux_enet(void)
121 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
124 static iomux_v3_cfg_t const usdhc3_pads[] = {
125 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
126 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
127 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
128 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
129 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
130 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
131 MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
132 MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
133 MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
134 MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
135 MX6_PAD_GPIO_18__SD3_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
136 MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
139 static void setup_iomux_uart(void)
141 imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
144 #ifdef CONFIG_FSL_ESDHC
145 static struct fsl_esdhc_cfg usdhc_cfg[1] = {
149 int board_mmc_getcd(struct mmc *mmc)
151 gpio_direction_input(IMX_GPIO_NR(6, 15));
152 return !gpio_get_value(IMX_GPIO_NR(6, 15));
155 int board_mmc_init(bd_t *bis)
157 imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
159 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
160 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
164 int mx6_rgmii_rework(struct phy_device *phydev)
168 /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
169 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
170 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
171 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
173 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
176 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
178 /* introduce tx clock delay */
179 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
180 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
182 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
187 int board_phy_config(struct phy_device *phydev)
189 mx6_rgmii_rework(phydev);
191 if (phydev->drv->config)
192 phydev->drv->config(phydev);
197 int board_eth_init(bd_t *bis)
201 return cpu_eth_init(bis);
204 #define BOARD_REV_B 0x200
205 #define BOARD_REV_A 0x100
207 static int mx6sabre_rev(void)
210 * Get Board ID information from OCOTP_GP1[15:8]
211 * i.MX6Q ARD RevA: 0x01
212 * i.MX6Q ARD RevB: 0x02
214 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
215 struct fuse_bank *bank = &ocotp->bank[4];
216 struct fuse_bank4_regs *fuse =
217 (struct fuse_bank4_regs *)bank->fuse_regs;
218 int reg = readl(&fuse->gp1);
221 switch (reg >> 8 & 0x0F) {
234 u32 get_board_rev(void)
236 int rev = mx6sabre_rev();
238 return (get_cpu_rev() & ~(0xF << 8)) | rev;
241 #if defined(CONFIG_VIDEO_IPUV3)
242 static void do_enable_hdmi(struct display_info_t const *dev)
244 imx_enable_hdmi_phy();
247 struct display_info_t const displays[] = {{
250 .pixfmt = IPU_PIX_FMT_RGB24,
251 .detect = detect_hdmi,
252 .enable = do_enable_hdmi,
266 .vmode = FB_VMODE_NONINTERLACED,
268 size_t display_count = ARRAY_SIZE(displays);
270 static void setup_display(void)
272 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
278 reg = readl(&mxc_ccm->chsccdr);
279 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
280 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
281 writel(reg, &mxc_ccm->chsccdr);
283 #endif /* CONFIG_VIDEO_IPUV3 */
286 * Do not overwrite the console
287 * Use always serial for U-Boot console
289 int overwrite_console(void)
294 int board_early_init_f(void)
297 #ifdef CONFIG_VIDEO_IPUV3
305 /* address of boot parameters */
306 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
308 /* I2C 2 and 3 setup - I2C 3 hw mux with EIM */
309 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
311 gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
312 imx_iomux_v3_setup_multiple_pads(i2c3_pads, ARRAY_SIZE(i2c3_pads));
313 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
315 gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
316 imx_iomux_v3_setup_multiple_pads(port_exp, ARRAY_SIZE(port_exp));
321 #ifdef CONFIG_MXC_SPI
322 int board_spi_cs_gpio(unsigned bus, unsigned cs)
324 return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1;
328 #ifdef CONFIG_CMD_BMODE
329 static const struct boot_mode board_boot_modes[] = {
330 /* 4 bit bus width */
331 {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
336 int board_late_init(void)
338 #ifdef CONFIG_CMD_BMODE
339 add_board_boot_modes(board_boot_modes);
347 int rev = mx6sabre_rev();
360 printf("Board: MX6Q-Sabreauto rev%s\n", revname);