2 * Copyright (C) 2012 Freescale Semiconductor, Inc.
4 * Author: Fabio Estevam <fabio.estevam@freescale.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
22 #include <asm/arch/clock.h>
23 #include <asm/arch/imx-regs.h>
24 #include <asm/arch/iomux.h>
25 #include <asm/arch/mx6q_pins.h>
26 #include <asm/errno.h>
28 #include <asm/imx-common/iomux-v3.h>
29 #include <asm/imx-common/boot_mode.h>
31 #include <fsl_esdhc.h>
34 #include <asm/arch/sys_proto.h>
36 DECLARE_GLOBAL_DATA_PTR;
38 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
39 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
40 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
42 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
43 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
44 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
46 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
47 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
51 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
56 iomux_v3_cfg_t const uart4_pads[] = {
57 MX6_PAD_KEY_COL0__UART4_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
58 MX6_PAD_KEY_ROW0__UART4_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
61 iomux_v3_cfg_t const enet_pads[] = {
62 MX6_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
63 MX6_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
64 MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
65 MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
66 MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
67 MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
68 MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
69 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
70 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
71 MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
72 MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
73 MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
74 MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
75 MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
76 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
79 static void setup_iomux_enet(void)
81 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
84 iomux_v3_cfg_t const usdhc3_pads[] = {
85 MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
86 MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
87 MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
88 MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
89 MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
90 MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
91 MX6_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
92 MX6_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
93 MX6_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
94 MX6_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
95 MX6_PAD_GPIO_18__USDHC3_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
96 MX6_PAD_NANDF_CS2__GPIO_6_15 | MUX_PAD_CTRL(NO_PAD_CTRL),
99 static void setup_iomux_uart(void)
101 imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
104 #ifdef CONFIG_FSL_ESDHC
105 struct fsl_esdhc_cfg usdhc_cfg[1] = {
109 int board_mmc_getcd(struct mmc *mmc)
111 gpio_direction_input(IMX_GPIO_NR(6, 15));
112 return !gpio_get_value(IMX_GPIO_NR(6, 15));
115 int board_mmc_init(bd_t *bis)
117 imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
119 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
120 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
124 int mx6_rgmii_rework(struct phy_device *phydev)
128 /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
129 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
130 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
131 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
133 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
136 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
138 /* introduce tx clock delay */
139 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
140 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
142 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
147 int board_phy_config(struct phy_device *phydev)
149 mx6_rgmii_rework(phydev);
151 if (phydev->drv->config)
152 phydev->drv->config(phydev);
157 int board_eth_init(bd_t *bis)
163 ret = cpu_eth_init(bis);
165 printf("FEC MXC: %s:failed\n", __func__);
170 #define BOARD_REV_B 0x200
171 #define BOARD_REV_A 0x100
173 static int mx6sabre_rev(void)
176 * Get Board ID information from OCOTP_GP1[15:8]
177 * i.MX6Q ARD RevA: 0x01
178 * i.MX6Q ARD RevB: 0x02
180 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
181 struct fuse_bank *bank = &ocotp->bank[4];
182 struct fuse_bank4_regs *fuse =
183 (struct fuse_bank4_regs *)bank->fuse_regs;
184 int reg = readl(&fuse->gp1);
187 switch (reg >> 8 & 0x0F) {
200 u32 get_board_rev(void)
202 int rev = mx6sabre_rev();
204 return (get_cpu_rev() & ~(0xF << 8)) | rev;
207 int board_early_init_f(void)
216 /* address of boot parameters */
217 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
222 #ifdef CONFIG_CMD_BMODE
223 static const struct boot_mode board_boot_modes[] = {
224 /* 4 bit bus width */
225 {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
230 int board_late_init(void)
232 #ifdef CONFIG_CMD_BMODE
233 add_board_boot_modes(board_boot_modes);
241 int rev = mx6sabre_rev();
254 printf("Board: MX6Q-Sabreauto rev%s\n", revname);