2 * Copyright (C) 2012 Freescale Semiconductor, Inc.
4 * Author: Fabio Estevam <fabio.estevam@freescale.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
22 #include <asm/arch/clock.h>
23 #include <asm/arch/imx-regs.h>
24 #include <asm/arch/iomux.h>
25 #include <asm/arch/mx6q_pins.h>
26 #include <asm/errno.h>
28 #include <asm/imx-common/iomux-v3.h>
29 #include <asm/imx-common/mxc_i2c.h>
30 #include <asm/imx-common/boot_mode.h>
32 #include <fsl_esdhc.h>
35 #include <asm/arch/sys_proto.h>
38 DECLARE_GLOBAL_DATA_PTR;
40 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
41 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
42 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
44 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
45 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
46 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
48 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
49 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
51 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
52 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
53 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
55 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
59 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
64 iomux_v3_cfg_t const uart4_pads[] = {
65 MX6_PAD_KEY_COL0__UART4_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
66 MX6_PAD_KEY_ROW0__UART4_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
69 iomux_v3_cfg_t const enet_pads[] = {
70 MX6_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
71 MX6_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
72 MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
73 MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
74 MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
75 MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
76 MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
77 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
78 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
79 MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
80 MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
81 MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
82 MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
83 MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
84 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
87 /* I2C2 PMIC, iPod, Tuner, Codec, Touch, HDMI EDID, MIPI CSI2 card */
88 struct i2c_pads_info i2c_pad_info1 = {
90 .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC,
91 .gpio_mode = MX6_PAD_EIM_EB2__GPIO_2_30 | PC,
92 .gp = IMX_GPIO_NR(2, 30)
95 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
96 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO_4_13 | PC,
97 .gp = IMX_GPIO_NR(4, 13)
102 * I2C3 MLB, Port Expanders (A, B, C), Video ADC, Light Sensor,
103 * Compass Sensor, Accelerometer, Res Touch
105 struct i2c_pads_info i2c_pad_info2 = {
107 .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC,
108 .gpio_mode = MX6_PAD_GPIO_3__GPIO_1_3 | PC,
109 .gp = IMX_GPIO_NR(1, 3)
112 .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
113 .gpio_mode = MX6_PAD_EIM_D18__GPIO_3_18 | PC,
114 .gp = IMX_GPIO_NR(3, 18)
118 iomux_v3_cfg_t const i2c3_pads[] = {
119 MX6_PAD_EIM_A24__GPIO_5_4 | MUX_PAD_CTRL(NO_PAD_CTRL),
122 iomux_v3_cfg_t const port_exp[] = {
123 MX6_PAD_SD2_DAT0__GPIO_1_15 | MUX_PAD_CTRL(NO_PAD_CTRL),
126 static void setup_iomux_enet(void)
128 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
131 iomux_v3_cfg_t const usdhc3_pads[] = {
132 MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
133 MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
134 MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
135 MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
136 MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
137 MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
138 MX6_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
139 MX6_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
140 MX6_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
141 MX6_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
142 MX6_PAD_GPIO_18__USDHC3_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
143 MX6_PAD_NANDF_CS2__GPIO_6_15 | MUX_PAD_CTRL(NO_PAD_CTRL),
146 static void setup_iomux_uart(void)
148 imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
151 #ifdef CONFIG_FSL_ESDHC
152 struct fsl_esdhc_cfg usdhc_cfg[1] = {
156 int board_mmc_getcd(struct mmc *mmc)
158 gpio_direction_input(IMX_GPIO_NR(6, 15));
159 return !gpio_get_value(IMX_GPIO_NR(6, 15));
162 int board_mmc_init(bd_t *bis)
164 imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
166 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
167 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
171 int mx6_rgmii_rework(struct phy_device *phydev)
175 /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
176 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
177 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
178 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
180 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
183 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
185 /* introduce tx clock delay */
186 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
187 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
189 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
194 int board_phy_config(struct phy_device *phydev)
196 mx6_rgmii_rework(phydev);
198 if (phydev->drv->config)
199 phydev->drv->config(phydev);
204 int board_eth_init(bd_t *bis)
210 ret = cpu_eth_init(bis);
212 printf("FEC MXC: %s:failed\n", __func__);
217 #define BOARD_REV_B 0x200
218 #define BOARD_REV_A 0x100
220 static int mx6sabre_rev(void)
223 * Get Board ID information from OCOTP_GP1[15:8]
224 * i.MX6Q ARD RevA: 0x01
225 * i.MX6Q ARD RevB: 0x02
227 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
228 struct fuse_bank *bank = &ocotp->bank[4];
229 struct fuse_bank4_regs *fuse =
230 (struct fuse_bank4_regs *)bank->fuse_regs;
231 int reg = readl(&fuse->gp1);
234 switch (reg >> 8 & 0x0F) {
247 u32 get_board_rev(void)
249 int rev = mx6sabre_rev();
251 return (get_cpu_rev() & ~(0xF << 8)) | rev;
254 int board_early_init_f(void)
263 /* address of boot parameters */
264 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
266 /* I2C 2 and 3 setup - I2C 3 hw mux with EIM */
267 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
269 gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
270 imx_iomux_v3_setup_multiple_pads(i2c3_pads, ARRAY_SIZE(i2c3_pads));
271 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
273 gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
274 imx_iomux_v3_setup_multiple_pads(port_exp, ARRAY_SIZE(port_exp));
279 #ifdef CONFIG_CMD_BMODE
280 static const struct boot_mode board_boot_modes[] = {
281 /* 4 bit bus width */
282 {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
287 int board_late_init(void)
289 #ifdef CONFIG_CMD_BMODE
290 add_board_boot_modes(board_boot_modes);
298 int rev = mx6sabre_rev();
311 printf("Board: MX6Q-Sabreauto rev%s\n", revname);