1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2014 Freescale Semiconductor, Inc.
4 * Jason Liu <r64343@freescale.com>
6 * Refer doc/README.imximage for more details about how-to configure
7 * and create imximage boot image
9 * The syntax is taken as close as possible with the kwbimage
16 * Boot Device : one of
17 * spi, sd (the board has no nand neither onenand)
22 * Device Configuration Data (DCD)
24 * Each entry must have the format:
25 * Addr-type Address Value
28 * Addr-type register length (1,2 or 4 bytes)
29 * Address absolute address of the register
30 * value value to be stored in the register
35 #ifdef CONFIG_MX6DL_LPDDR2
38 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 */
39 DATA 4 0x020E04bc 0x00003028
40 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 */
41 DATA 4 0x020E04c0 0x00003028
42 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 */
43 DATA 4 0x020E04c4 0x00003028
44 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 */
45 DATA 4 0x020E04c8 0x00003028
46 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4 */
47 DATA 4 0x020E04cc 0x00003028
48 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5 */
49 DATA 4 0x020E04d0 0x00003028
50 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6 */
51 DATA 4 0x020E04d4 0x00003028
52 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7 */
53 DATA 4 0x020E04d8 0x00003028
55 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 */
56 DATA 4 0x020E0470 0x00000038
57 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 */
58 DATA 4 0x020E0474 0x00000038
59 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 */
60 DATA 4 0x020E0478 0x00000038
61 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 */
62 DATA 4 0x020E047c 0x00000038
63 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4 */
64 DATA 4 0x020E0480 0x00000038
65 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5 */
66 DATA 4 0x020E0484 0x00000038
67 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6 */
68 DATA 4 0x020E0488 0x00000038
69 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7 */
70 DATA 4 0x020E048c 0x00000038
71 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS */
72 DATA 4 0x020E0464 0x00000038
73 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS */
74 DATA 4 0x020E0490 0x00000038
75 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 */
76 DATA 4 0x020E04ac 0x00000038
77 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1 */
78 DATA 4 0x020E04b0 0x00000038
79 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET */
80 DATA 4 0x020E0494 0x00000038
81 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0 */
82 DATA 4 0x020E04a4 0x00000038
83 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1 */
84 DATA 4 0x020E04a8 0x00000038
86 * IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2
87 * DSE can be configured using Group Control Register:
88 * IOMUXC_SW_PAD_CTL_GRP_CTLDS
90 DATA 4 0x020E04a0 0x00000000
91 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0 */
92 DATA 4 0x020E04b4 0x00000038
93 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1 */
94 DATA 4 0x020E04b8 0x00000038
95 /* IOMUXC_SW_PAD_CTL_GRP_B0DS */
96 DATA 4 0x020E0764 0x00000038
97 /* IOMUXC_SW_PAD_CTL_GRP_B1DS */
98 DATA 4 0x020E0770 0x00000038
99 /* IOMUXC_SW_PAD_CTL_GRP_B2DS */
100 DATA 4 0x020E0778 0x00000038
101 /* IOMUXC_SW_PAD_CTL_GRP_B3DS */
102 DATA 4 0x020E077c 0x00000038
103 /* IOMUXC_SW_PAD_CTL_GRP_B4DS */
104 DATA 4 0x020E0780 0x00000038
105 /* IOMUXC_SW_PAD_CTL_GRP_B5DS */
106 DATA 4 0x020E0784 0x00000038
107 /* IOMUXC_SW_PAD_CTL_GRP_B6DS */
108 DATA 4 0x020E078c 0x00000038
109 /* IOMUXC_SW_PAD_CTL_GRP_B7DS */
110 DATA 4 0x020E0748 0x00000038
111 /* IOMUXC_SW_PAD_CTL_GRP_ADDDS */
112 DATA 4 0x020E074c 0x00000038
113 /* IOMUXC_SW_PAD_CTL_GRP_CTLDS */
114 DATA 4 0x020E076c 0x00000038
115 /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL */
116 DATA 4 0x020E0750 0x00020000
117 /* IOMUXC_SW_PAD_CTL_GRP_DDRPKE */
118 DATA 4 0x020E0754 0x00000000
119 /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE */
120 DATA 4 0x020E0760 0x00020000
121 /* IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE */
122 DATA 4 0x020E0774 0x00080000
125 * DDR Controller Registers
127 * Manufacturer: Mocron
128 * Device Part Number: MT42L64M64D2KH-18
129 * Clock Freq.: 528MHz
130 * MMDC channels: Both MMDC0, MMDC1
131 *Density per CS in Gb: 256M
132 * Chip Selects used: 2
139 /* MMDC_P0_BASE_ADDR = 0x021b0000 */
140 /* MMDC_P1_BASE_ADDR = 0x021b4000 */
142 /* MMDC0_MDSCR, set the Configuration request bit during MMDC set up */
143 DATA 4 0x021b001c 0x00008000
145 /* MMDC0_MDSCR, set the Configuration request bit during MMDC set up */
146 DATA 4 0x021b401c 0x00008000
148 /*LPDDR2 ZQ params */
149 DATA 4 0x021b085c 0x1b5f01ff
150 DATA 4 0x021b485c 0x1b5f01ff
152 /* Calibration setup. */
153 /* DDR_PHY_P0_MPZQHWCTRL, enable on time ZQ calibration */
154 DATA 4 0x021b0800 0xa1390003
156 /*ca bus abs delay */
157 DATA 4 0x021b0890 0x00400000
158 /*ca bus abs delay */
159 DATA 4 0x021b4890 0x00400000
160 /* values of 20,40,50,60,7f tried. no difference seen */
162 /* DDR_PHY_P1_MPWRCADL */
163 DATA 4 0x021b48bc 0x00055555
166 DATA 4 0x021b08b8 0x00000800
168 DATA 4 0x021b48b8 0x00000800
170 /* DDR_PHY_P0_MPREDQBY0DL3 */
171 DATA 4 0x021b081c 0x33333333
172 /* DDR_PHY_P0_MPREDQBY1DL3 */
173 DATA 4 0x021b0820 0x33333333
174 /* DDR_PHY_P0_MPREDQBY2DL3 */
175 DATA 4 0x021b0824 0x33333333
176 /* DDR_PHY_P0_MPREDQBY3DL3 */
177 DATA 4 0x021b0828 0x33333333
178 /* DDR_PHY_P1_MPREDQBY0DL3 */
179 DATA 4 0x021b481c 0x33333333
180 /* DDR_PHY_P1_MPREDQBY1DL3 */
181 DATA 4 0x021b4820 0x33333333
182 /* DDR_PHY_P1_MPREDQBY2DL3 */
183 DATA 4 0x021b4824 0x33333333
184 /* DDR_PHY_P1_MPREDQBY3DL3 */
185 DATA 4 0x021b4828 0x33333333
188 * Read and write data delay, per byte.
189 * For optimized DDR operation it is recommended to run mmdc_calibration
190 * on your board, and replace 4 delay register assigns with resulted values
192 * a. DQS gating is not relevant for LPDDR2. DSQ gating calibration section
193 * should be skipped, or the write/read calibration comming after that
195 * b. The calibration code that runs for both MMDC0 & MMDC1 should be used.
198 DATA 4 0x021b0848 0x4b4b524f
199 DATA 4 0x021b4848 0x494f4c44
201 DATA 4 0x021b0850 0x3c3d303c
202 DATA 4 0x021b4850 0x3c343d38
205 DATA 4 0x021b083c 0x20000000
206 DATA 4 0x021b0840 0x0
207 DATA 4 0x021b483c 0x20000000
208 DATA 4 0x021b4840 0x0
211 DATA 4 0x021b0858 0xa00
213 DATA 4 0x021b4858 0xa00
216 DATA 4 0x021b08b8 0x00000800
218 DATA 4 0x021b48b8 0x00000800
219 /* Calibration setup end */
221 /* Channel0 - startng address 0x80000000 */
223 DATA 4 0x021b000c 0x34386145
226 DATA 4 0x021b0004 0x00020036
228 DATA 4 0x021b0010 0x00100c83
230 DATA 4 0x021b0014 0x000000Dc
232 DATA 4 0x021b0018 0x0000174C
234 DATA 4 0x021b002c 0x0f9f26d2
236 DATA 4 0x021b0030 0x009f0e10
238 DATA 4 0x021b0038 0x00190778
240 DATA 4 0x021b0008 0x00000000
243 DATA 4 0x021b0040 0x0000005f
245 DATA 4 0x021b0404 0x0000000f
248 DATA 4 0x021b0000 0xc3010000
250 /* Channel1 - starting address 0x10000000 */
252 DATA 4 0x021b400c 0x34386145
255 DATA 4 0x021b4004 0x00020036
257 DATA 4 0x021b4010 0x00100c83
259 DATA 4 0x021b4014 0x000000Dc
261 DATA 4 0x021b4018 0x0000174C
263 DATA 4 0x021b402c 0x0f9f26d2
265 DATA 4 0x021b4030 0x009f0e10
267 DATA 4 0x021b4038 0x00190778
269 DATA 4 0x021b4008 0x00000000
272 DATA 4 0x021b4040 0x0000003f
275 DATA 4 0x021b4000 0xc3010000
277 /* Channel0 : Configure DDR device:*/
278 /* MRW: BA=0 CS=0 MR_ADDR=63 MR_OP=0 */
279 DATA 4 0x021b001c 0x003f8030
280 /* MRW: BA=0 CS=0 MR_ADDR=10 MR_OP=ff */
281 DATA 4 0x021b001c 0xff0a8030
282 /* MRW: BA=0 CS=0 MR_ADDR=1 MR_OP=a2 */
283 DATA 4 0x021b001c 0xa2018030
284 /* MRW: BA=0 CS=0 MR_ADDR=2 MR_OP=6. tcl=8, tcwl=4 */
285 DATA 4 0x021b001c 0x06028030
286 /* MRW: BA=0 CS=0 MR_ADDR=3 MR_OP=2.drive=240/6 */
287 DATA 4 0x021b001c 0x01038030
289 /* Channel1 : Configure DDR device:*/
290 /* MRW: BA=0 CS=0 MR_ADDR=63 MR_OP=0 */
291 DATA 4 0x021b401c 0x003f8030
292 /* MRW: BA=0 CS=0 MR_ADDR=10 MR_OP=ff */
293 DATA 4 0x021b401c 0xff0a8030
294 /* MRW: BA=0 CS=0 MR_ADDR=1 MR_OP=a2 */
295 DATA 4 0x021b401c 0xa2018030
296 /* MRW: BA=0 CS=0 MR_ADDR=2 MR_OP=6. tcl=8, tcwl=4 */
297 DATA 4 0x021b401c 0x06028030
298 /* MRW: BA=0 CS=0 MR_ADDR=3 MR_OP=2.drive=240/6 */
299 DATA 4 0x021b401c 0x01038030
302 DATA 4 0x021b0020 0x00005800
304 DATA 4 0x021b4020 0x00005800
306 /* DDR_PHY_P0_MPODTCTRL */
307 DATA 4 0x021b0818 0x0
308 /* DDR_PHY_P1_MPODTCTRL */
309 DATA 4 0x021b4818 0x0
312 * calibration values based on calibration compare of 0x00ffff00:
313 * Note, these calibration values are based on Freescale's board
314 * May need to run calibration on target board to fine tune these
317 /* DDR_PHY_P0_MPZQHWCTRL, enable automatic ZQ calibration */
318 DATA 4 0x021b0800 0xa1310003
320 /* DDR_PHY_P0_MPMUR0, frc_msr */
321 DATA 4 0x021b08b8 0x00000800
322 /* DDR_PHY_P1_MPMUR0, frc_msr */
323 DATA 4 0x021b48b8 0x00000800
326 * MMDC0_MDSCR, clear this register
327 * (especially the configuration bit as initialization is complete)
329 DATA 4 0x021b001c 0x00000000
331 * MMDC0_MDSCR, clear this register
332 * (especially the configuration bit as initialization is complete)
334 DATA 4 0x021b401c 0x00000000
336 DATA 4 0x020c4068 0x00C03F3F
337 DATA 4 0x020c406c 0x0030FC03
338 DATA 4 0x020c4070 0x0FFFC000
339 DATA 4 0x020c4074 0x3FF00000
340 DATA 4 0x020c4078 0x00FFF300
341 DATA 4 0x020c407c 0x0F0000C3
342 DATA 4 0x020c4080 0x000003FF
344 DATA 4 0x020e0010 0xF00000CF
345 DATA 4 0x020e0018 0x007F007F
346 DATA 4 0x020e001c 0x007F007F
348 #else /* CONFIG_MX6DL_LPDDR2 */
350 DATA 4 0x020e0798 0x000c0000
351 DATA 4 0x020e0758 0x00000000
352 DATA 4 0x020e0588 0x00000030
353 DATA 4 0x020e0594 0x00000030
354 DATA 4 0x020e056c 0x00000030
355 DATA 4 0x020e0578 0x00000030
356 DATA 4 0x020e074c 0x00000030
357 DATA 4 0x020e057c 0x00000030
358 DATA 4 0x020e0590 0x00003000
359 DATA 4 0x020e0598 0x00003000
360 DATA 4 0x020e058c 0x00000000
361 DATA 4 0x020e059c 0x00003030
362 DATA 4 0x020e05a0 0x00003030
363 DATA 4 0x020e078c 0x00000030
364 DATA 4 0x020e0750 0x00020000
365 DATA 4 0x020e05a8 0x00000030
366 DATA 4 0x020e05b0 0x00000030
367 DATA 4 0x020e0524 0x00000030
368 DATA 4 0x020e051c 0x00000030
369 DATA 4 0x020e0518 0x00000030
370 DATA 4 0x020e050c 0x00000030
371 DATA 4 0x020e05b8 0x00000030
372 DATA 4 0x020e05c0 0x00000030
373 DATA 4 0x020e0774 0x00020000
374 DATA 4 0x020e0784 0x00000030
375 DATA 4 0x020e0788 0x00000030
376 DATA 4 0x020e0794 0x00000030
377 DATA 4 0x020e079c 0x00000030
378 DATA 4 0x020e07a0 0x00000030
379 DATA 4 0x020e07a4 0x00000030
380 DATA 4 0x020e07a8 0x00000030
381 DATA 4 0x020e0748 0x00000030
382 DATA 4 0x020e05ac 0x00000030
383 DATA 4 0x020e05b4 0x00000030
384 DATA 4 0x020e0528 0x00000030
385 DATA 4 0x020e0520 0x00000030
386 DATA 4 0x020e0514 0x00000030
387 DATA 4 0x020e0510 0x00000030
388 DATA 4 0x020e05bc 0x00000030
389 DATA 4 0x020e05c4 0x00000030
391 DATA 4 0x021b0800 0xa1390003
392 DATA 4 0x021b4800 0xa1390003
393 DATA 4 0x021b080c 0x001F001F
394 DATA 4 0x021b0810 0x001F001F
395 DATA 4 0x021b480c 0x00370037
396 DATA 4 0x021b4810 0x00370037
397 DATA 4 0x021b083c 0x422f0220
398 DATA 4 0x021b0840 0x021f0219
399 DATA 4 0x021b483C 0x422f0220
400 DATA 4 0x021b4840 0x022d022f
401 DATA 4 0x021b0848 0x47494b49
402 DATA 4 0x021b4848 0x48484c47
403 DATA 4 0x021b0850 0x39382b2f
404 DATA 4 0x021b4850 0x2f35312c
405 DATA 4 0x021b081c 0x33333333
406 DATA 4 0x021b0820 0x33333333
407 DATA 4 0x021b0824 0x33333333
408 DATA 4 0x021b0828 0x33333333
409 DATA 4 0x021b481c 0x33333333
410 DATA 4 0x021b4820 0x33333333
411 DATA 4 0x021b4824 0x33333333
412 DATA 4 0x021b4828 0x33333333
413 DATA 4 0x021b08b8 0x00000800
414 DATA 4 0x021b48b8 0x00000800
415 DATA 4 0x021b0004 0x0002002d
416 DATA 4 0x021b0008 0x00333030
418 DATA 4 0x021b000c 0x40445323
419 DATA 4 0x021b0010 0xb66e8c63
421 DATA 4 0x021b0014 0x01ff00db
422 DATA 4 0x021b0018 0x00081740
423 DATA 4 0x021b001c 0x00008000
424 DATA 4 0x021b002c 0x000026d2
425 DATA 4 0x021b0030 0x00440e21
426 #ifdef CONFIG_DDR_32BIT
427 DATA 4 0x021b0040 0x00000017
428 DATA 4 0x021b0000 0xc3190000
430 DATA 4 0x021b0040 0x00000027
431 DATA 4 0x021b0000 0xc31a0000
433 DATA 4 0x021b001c 0x04008032
434 DATA 4 0x021b001c 0x0400803a
435 DATA 4 0x021b001c 0x00008033
436 DATA 4 0x021b001c 0x0000803b
437 DATA 4 0x021b001c 0x00428031
438 DATA 4 0x021b001c 0x00428039
439 DATA 4 0x021b001c 0x07208030
440 DATA 4 0x021b001c 0x07208038
441 DATA 4 0x021b001c 0x04008040
442 DATA 4 0x021b001c 0x04008048
443 DATA 4 0x021b0020 0x00005800
444 DATA 4 0x021b0818 0x00000007
445 DATA 4 0x021b4818 0x00000007
446 DATA 4 0x021b0004 0x0002556d
447 DATA 4 0x021b4004 0x00011006
448 DATA 4 0x021b001c 0x00000000
450 DATA 4 0x020c4068 0x00C03F3F
451 DATA 4 0x020c406c 0x0030FC03
452 DATA 4 0x020c4070 0x0FFFC000
453 DATA 4 0x020c4074 0x3FF00000
454 DATA 4 0x020c4078 0x00FFF300
455 DATA 4 0x020c407c 0x0F0000C3
456 DATA 4 0x020c4080 0x000003FF
458 DATA 4 0x020e0010 0xF00000CF
459 DATA 4 0x020e0018 0x007F007F
460 DATA 4 0x020e001c 0x007F007F
461 #endif /* CONFIG_MX6DL_LPDDR2 */