2 * (C) Copyright 2011 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/arch/imx-regs.h>
26 #include <asm/arch/mx5x_pins.h>
27 #include <asm/arch/sys_proto.h>
28 #include <asm/arch/crm_regs.h>
29 #include <asm/arch/iomux.h>
30 #include <asm/errno.h>
33 #include <fsl_esdhc.h>
36 DECLARE_GLOBAL_DATA_PTR;
42 size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
43 size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
45 gd->ram_size = size1 + size2;
49 void dram_init_banksize(void)
51 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
52 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
54 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
55 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
58 static void setup_iomux_uart(void)
61 mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_ALT2);
62 mxc_iomux_set_pad(MX53_PIN_CSI0_D11,
63 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
64 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
65 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
66 PAD_CTL_ODE_OPENDRAIN_ENABLE);
67 mxc_iomux_set_input(MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x1);
70 mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT2);
71 mxc_iomux_set_pad(MX53_PIN_CSI0_D10,
72 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
73 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
74 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
75 PAD_CTL_ODE_OPENDRAIN_ENABLE);
78 static void setup_iomux_fec(void)
81 mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0);
82 mxc_iomux_set_pad(MX53_PIN_FEC_MDIO,
83 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
84 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
85 PAD_CTL_22K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE);
86 mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT, 0x1);
89 mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0);
90 mxc_iomux_set_pad(MX53_PIN_FEC_MDC, PAD_CTL_DRV_HIGH);
93 mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0);
94 mxc_iomux_set_pad(MX53_PIN_FEC_RXD1,
95 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
98 mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0);
99 mxc_iomux_set_pad(MX53_PIN_FEC_RXD0,
100 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
103 mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0);
104 mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, PAD_CTL_DRV_HIGH);
107 mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0);
108 mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, PAD_CTL_DRV_HIGH);
111 mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0);
112 mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, PAD_CTL_DRV_HIGH);
115 mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0);
116 mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK,
117 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
120 mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0);
121 mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER,
122 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
125 mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0);
126 mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV,
127 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
130 #ifdef CONFIG_FSL_ESDHC
131 struct fsl_esdhc_cfg esdhc_cfg[1] = {
132 {MMC_SDHC1_BASE_ADDR, 1},
135 int board_mmc_getcd(u8 *cd, struct mmc *mmc)
137 mxc_request_iomux(MX53_PIN_EIM_DA13, IOMUX_CONFIG_ALT1);
138 *cd = gpio_get_value(77); /*GPIO3_13*/
143 int board_mmc_init(bd_t *bis)
148 for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
151 mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
152 mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
153 mxc_request_iomux(MX53_PIN_SD1_DATA0,
155 mxc_request_iomux(MX53_PIN_SD1_DATA1,
157 mxc_request_iomux(MX53_PIN_SD1_DATA2,
159 mxc_request_iomux(MX53_PIN_SD1_DATA3,
161 mxc_request_iomux(MX53_PIN_EIM_DA13,
164 mxc_iomux_set_pad(MX53_PIN_SD1_CMD,
165 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
166 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
167 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
168 mxc_iomux_set_pad(MX53_PIN_SD1_CLK,
169 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
170 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
172 mxc_iomux_set_pad(MX53_PIN_SD1_DATA0,
173 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
174 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
175 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
176 mxc_iomux_set_pad(MX53_PIN_SD1_DATA1,
177 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
178 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
179 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
180 mxc_iomux_set_pad(MX53_PIN_SD1_DATA2,
181 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
182 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
183 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
184 mxc_iomux_set_pad(MX53_PIN_SD1_DATA3,
185 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
186 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
187 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
191 printf("Warning: you configured more ESDHC controller"
192 "(%d) as supported by the board(1)\n",
193 CONFIG_SYS_FSL_ESDHC_NUM);
196 status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
203 int board_early_init_f(void)
213 /* address of boot parameters */
214 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
221 puts("Board: MX53SMD\n");