1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2011 Freescale Semiconductor, Inc.
8 #include <asm/arch/imx-regs.h>
9 #include <asm/arch/sys_proto.h>
10 #include <asm/arch/crm_regs.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/iomux-mx53.h>
13 #include <linux/errno.h>
16 #include <fsl_esdhc_imx.h>
19 DECLARE_GLOBAL_DATA_PTR;
25 size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
26 size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
28 gd->ram_size = size1 + size2;
32 int dram_init_banksize(void)
34 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
35 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
37 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
38 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
43 #define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
44 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
46 static void setup_iomux_uart(void)
48 static const iomux_v3_cfg_t uart_pads[] = {
49 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, UART_PAD_CTRL),
50 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, UART_PAD_CTRL),
53 imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
56 static void setup_iomux_fec(void)
58 static const iomux_v3_cfg_t fec_pads[] = {
59 NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
60 PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
61 NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
62 NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
63 PAD_CTL_HYS | PAD_CTL_PKE),
64 NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
65 PAD_CTL_HYS | PAD_CTL_PKE),
66 NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
67 NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
68 NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
69 NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
70 PAD_CTL_HYS | PAD_CTL_PKE),
71 NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
72 PAD_CTL_HYS | PAD_CTL_PKE),
73 NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
74 PAD_CTL_HYS | PAD_CTL_PKE),
77 imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
80 #ifdef CONFIG_FSL_ESDHC_IMX
81 struct fsl_esdhc_cfg esdhc_cfg[1] = {
82 {MMC_SDHC1_BASE_ADDR},
85 int board_mmc_getcd(struct mmc *mmc)
87 imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA13__GPIO3_13);
88 gpio_direction_input(IMX_GPIO_NR(3, 13));
89 return !gpio_get_value(IMX_GPIO_NR(3, 13));
92 #define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
94 #define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
97 int board_mmc_init(bd_t *bis)
99 static const iomux_v3_cfg_t sd1_pads[] = {
100 NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
101 NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
102 NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
103 NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
104 NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
105 NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
106 MX53_PAD_EIM_DA13__GPIO3_13,
112 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
114 for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
117 imx_iomux_v3_setup_multiple_pads(sd1_pads,
118 ARRAY_SIZE(sd1_pads));
122 printf("Warning: you configured more ESDHC controller"
123 "(%d) as supported by the board(1)\n",
124 CONFIG_SYS_FSL_ESDHC_NUM);
127 ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
136 int board_early_init_f(void)
146 /* address of boot parameters */
147 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
154 puts("Board: MX53SMD\n");