2 * Copyright (C) 2011 Freescale Semiconductor, Inc.
3 * Jason Liu <r64343@freescale.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/arch/imx-regs.h>
27 #include <asm/arch/mx5x_pins.h>
28 #include <asm/arch/sys_proto.h>
29 #include <asm/arch/crm_regs.h>
30 #include <asm/arch/clock.h>
31 #include <asm/arch/iomux.h>
32 #include <asm/arch/clock.h>
33 #include <asm/errno.h>
37 #include <fsl_esdhc.h>
40 #include <dialog_pmic.h>
43 DECLARE_GLOBAL_DATA_PTR;
49 size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
50 size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
52 gd->ram_size = size1 + size2;
56 void dram_init_banksize(void)
58 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
59 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
61 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
62 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
65 u32 get_board_rev(void)
67 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
68 struct fuse_bank *bank = &iim->bank[0];
69 struct fuse_bank0_regs *fuse =
70 (struct fuse_bank0_regs *)bank->fuse_regs;
72 int rev = readl(&fuse->gp[6]);
74 return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
77 static void setup_iomux_uart(void)
80 mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_ALT2);
81 mxc_iomux_set_pad(MX53_PIN_CSI0_D11,
82 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
83 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
84 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
85 PAD_CTL_ODE_OPENDRAIN_ENABLE);
86 mxc_iomux_set_input(MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x1);
89 mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT2);
90 mxc_iomux_set_pad(MX53_PIN_CSI0_D10,
91 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
92 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
93 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
94 PAD_CTL_ODE_OPENDRAIN_ENABLE);
97 #ifdef CONFIG_USB_EHCI_MX5
98 int board_ehci_hcd_init(int port)
100 /* request VBUS power enable pin, GPIO[8}, gpio7 */
101 mxc_request_iomux(MX53_PIN_ATA_DA_2, IOMUX_CONFIG_ALT1);
102 gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_2), 0);
103 gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_2), 1);
108 static void setup_iomux_fec(void)
111 mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0);
112 mxc_iomux_set_pad(MX53_PIN_FEC_MDIO,
113 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
114 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
115 PAD_CTL_22K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE);
116 mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT, 0x1);
119 mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0);
120 mxc_iomux_set_pad(MX53_PIN_FEC_MDC, PAD_CTL_DRV_HIGH);
123 mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0);
124 mxc_iomux_set_pad(MX53_PIN_FEC_RXD1,
125 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
128 mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0);
129 mxc_iomux_set_pad(MX53_PIN_FEC_RXD0,
130 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
133 mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0);
134 mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, PAD_CTL_DRV_HIGH);
137 mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0);
138 mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, PAD_CTL_DRV_HIGH);
141 mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0);
142 mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, PAD_CTL_DRV_HIGH);
145 mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0);
146 mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK,
147 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
150 mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0);
151 mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER,
152 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
155 mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0);
156 mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV,
157 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
160 #ifdef CONFIG_FSL_ESDHC
161 struct fsl_esdhc_cfg esdhc_cfg[2] = {
162 {MMC_SDHC1_BASE_ADDR, 1},
163 {MMC_SDHC3_BASE_ADDR, 1},
166 int board_mmc_getcd(struct mmc *mmc)
168 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
171 mxc_request_iomux(MX53_PIN_EIM_DA11, IOMUX_CONFIG_ALT1);
172 gpio_direction_input(75);
173 mxc_request_iomux(MX53_PIN_EIM_DA13, IOMUX_CONFIG_ALT1);
174 gpio_direction_input(77);
176 if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
177 ret = !gpio_get_value(77); /* GPIO3_13 */
179 ret = !gpio_get_value(75); /* GPIO3_11 */
184 int board_mmc_init(bd_t *bis)
189 for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
192 mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
193 mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
194 mxc_request_iomux(MX53_PIN_SD1_DATA0,
196 mxc_request_iomux(MX53_PIN_SD1_DATA1,
198 mxc_request_iomux(MX53_PIN_SD1_DATA2,
200 mxc_request_iomux(MX53_PIN_SD1_DATA3,
202 mxc_request_iomux(MX53_PIN_EIM_DA13,
205 mxc_iomux_set_pad(MX53_PIN_SD1_CMD,
206 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
207 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
208 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
209 mxc_iomux_set_pad(MX53_PIN_SD1_CLK,
210 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
211 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
213 mxc_iomux_set_pad(MX53_PIN_SD1_DATA0,
214 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
215 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
216 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
217 mxc_iomux_set_pad(MX53_PIN_SD1_DATA1,
218 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
219 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
220 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
221 mxc_iomux_set_pad(MX53_PIN_SD1_DATA2,
222 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
223 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
224 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
225 mxc_iomux_set_pad(MX53_PIN_SD1_DATA3,
226 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
227 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
228 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
231 mxc_request_iomux(MX53_PIN_ATA_RESET_B,
233 mxc_request_iomux(MX53_PIN_ATA_IORDY,
235 mxc_request_iomux(MX53_PIN_ATA_DATA8,
237 mxc_request_iomux(MX53_PIN_ATA_DATA9,
239 mxc_request_iomux(MX53_PIN_ATA_DATA10,
241 mxc_request_iomux(MX53_PIN_ATA_DATA11,
243 mxc_request_iomux(MX53_PIN_ATA_DATA0,
245 mxc_request_iomux(MX53_PIN_ATA_DATA1,
247 mxc_request_iomux(MX53_PIN_ATA_DATA2,
249 mxc_request_iomux(MX53_PIN_ATA_DATA3,
251 mxc_request_iomux(MX53_PIN_EIM_DA11,
254 mxc_iomux_set_pad(MX53_PIN_ATA_RESET_B,
255 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
256 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
257 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
258 mxc_iomux_set_pad(MX53_PIN_ATA_IORDY,
259 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
260 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
262 mxc_iomux_set_pad(MX53_PIN_ATA_DATA8,
263 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
264 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
265 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
266 mxc_iomux_set_pad(MX53_PIN_ATA_DATA9,
267 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
268 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
269 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
270 mxc_iomux_set_pad(MX53_PIN_ATA_DATA10,
271 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
272 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
273 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
274 mxc_iomux_set_pad(MX53_PIN_ATA_DATA11,
275 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
276 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
277 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
278 mxc_iomux_set_pad(MX53_PIN_ATA_DATA0,
279 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
280 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
281 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
282 mxc_iomux_set_pad(MX53_PIN_ATA_DATA1,
283 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
284 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
285 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
286 mxc_iomux_set_pad(MX53_PIN_ATA_DATA2,
287 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
288 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
289 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
290 mxc_iomux_set_pad(MX53_PIN_ATA_DATA3,
291 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
292 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
293 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
297 printf("Warning: you configured more ESDHC controller"
298 "(%d) as supported by the board(2)\n",
299 CONFIG_SYS_FSL_ESDHC_NUM);
302 status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
309 static void setup_iomux_i2c(void)
312 mxc_request_iomux(MX53_PIN_CSI0_D8,
313 IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
314 mxc_iomux_set_input(MX53_I2C1_IPP_SDA_IN_SELECT_INPUT,
316 mxc_iomux_set_pad(MX53_PIN_CSI0_D8,
317 PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
318 PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE |
320 PAD_CTL_ODE_OPENDRAIN_ENABLE);
322 mxc_request_iomux(MX53_PIN_CSI0_D9,
323 IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
324 mxc_iomux_set_input(MX53_I2C1_IPP_SCL_IN_SELECT_INPUT,
326 mxc_iomux_set_pad(MX53_PIN_CSI0_D9,
327 PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
328 PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE |
330 PAD_CTL_ODE_OPENDRAIN_ENABLE);
333 static int power_init(void)
339 if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR)) {
343 /* Set VDDA to 1.25V */
344 val = DA9052_BUCKCORE_BCOREEN | DA_BUCKCORE_VBCORE_1_250V;
345 ret = pmic_reg_write(p, DA9053_BUCKCORE_REG, val);
347 ret |= pmic_reg_read(p, DA9053_SUPPLY_REG, &val);
348 val |= DA9052_SUPPLY_VBCOREGO;
349 ret |= pmic_reg_write(p, DA9053_SUPPLY_REG, val);
351 /* Set Vcc peripheral to 1.30V */
352 ret |= pmic_reg_write(p, DA9053_BUCKPRO_REG, 0x62);
353 ret |= pmic_reg_write(p, DA9053_SUPPLY_REG, 0x62);
356 if (!i2c_probe(CONFIG_SYS_FSL_PMIC_I2C_ADDR)) {
360 /* Set VDDGP to 1.25V for 1GHz on SW1 */
361 pmic_reg_read(p, REG_SW_0, &val);
362 val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_250V_MC34708;
363 ret = pmic_reg_write(p, REG_SW_0, val);
365 /* Set VCC as 1.30V on SW2 */
366 pmic_reg_read(p, REG_SW_1, &val);
367 val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_300V_MC34708;
368 ret |= pmic_reg_write(p, REG_SW_1, val);
370 /* Set global reset timer to 4s */
371 pmic_reg_read(p, REG_POWER_CTL2, &val);
372 val = (val & ~TIMER_MASK_MC34708) | TIMER_4S_MC34708;
373 ret |= pmic_reg_write(p, REG_POWER_CTL2, val);
375 /* Set VUSBSEL and VUSBEN for USB PHY supply*/
376 pmic_reg_read(p, REG_MODE_0, &val);
377 val |= (VUSBSEL_MC34708 | VUSBEN_MC34708);
378 ret |= pmic_reg_write(p, REG_MODE_0, val);
380 /* Set SWBST to 5V in auto mode */
382 ret |= pmic_reg_write(p, SWBST_CTRL, val);
388 static void clock_1GHz(void)
391 u32 ref_clk = CONFIG_SYS_MX5_HCLK;
393 * After increasing voltage to 1.25V, we can switch
394 * CPU clock to 1GHz and DDR to 400MHz safely
396 ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK);
398 printf("CPU: Switch CPU clock to 1GHZ failed\n");
400 ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK);
401 ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK);
403 printf("CPU: Switch DDR clock to 400MHz failed\n");
406 int board_early_init_f(void)
414 int print_cpuinfo(void)
418 cpurev = get_cpu_rev();
419 printf("CPU: Freescale i.MX%x family rev%d.%d at %d MHz\n",
420 (cpurev & 0xFF000) >> 12,
421 (cpurev & 0x000F0) >> 4,
422 (cpurev & 0x0000F) >> 0,
423 mxc_get_clock(MXC_ARM_CLK) / 1000000);
424 printf("Reset cause: %s\n", get_reset_cause());
428 #ifdef CONFIG_BOARD_LATE_INIT
429 int board_late_init(void)
442 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
444 mxc_set_sata_internal_clock();
451 puts("Board: MX53 LOCO\n");