1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2010 Freescale Semiconductor, Inc.
8 #include <asm/arch/imx-regs.h>
9 #include <asm/arch/sys_proto.h>
10 #include <asm/arch/crm_regs.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/iomux-mx53.h>
13 #include <linux/errno.h>
14 #include <asm/mach-imx/boot_mode.h>
18 #include <fsl_esdhc_imx.h>
19 #include <power/pmic.h>
24 DECLARE_GLOBAL_DATA_PTR;
28 /* dram_init must store complete ramsize in gd->ram_size */
29 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
34 #define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
35 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
37 static void setup_iomux_uart(void)
39 static const iomux_v3_cfg_t uart_pads[] = {
40 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, UART_PAD_CTRL),
41 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, UART_PAD_CTRL),
44 imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
47 #define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
48 PAD_CTL_HYS | PAD_CTL_ODE)
50 static void setup_i2c(unsigned int port_number)
52 static const iomux_v3_cfg_t i2c1_pads[] = {
53 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT8__I2C1_SDA, I2C_PAD_CTRL),
54 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT9__I2C1_SCL, I2C_PAD_CTRL),
57 static const iomux_v3_cfg_t i2c2_pads[] = {
58 NEW_PAD_CTRL(MX53_PAD_KEY_ROW3__I2C2_SDA, I2C_PAD_CTRL),
59 NEW_PAD_CTRL(MX53_PAD_KEY_COL3__I2C2_SCL, I2C_PAD_CTRL),
62 switch (port_number) {
64 imx_iomux_v3_setup_multiple_pads(i2c1_pads,
65 ARRAY_SIZE(i2c1_pads));
68 imx_iomux_v3_setup_multiple_pads(i2c2_pads,
69 ARRAY_SIZE(i2c2_pads));
72 printf("Warning: Wrong I2C port number\n");
83 ret = pmic_init(I2C_0);
87 p = pmic_get("FSL_PMIC");
91 /* Set VDDA to 1.25V */
92 pmic_reg_read(p, REG_SW_2, &val);
95 pmic_reg_write(p, REG_SW_2, val);
98 * Need increase VCC and VDDA to 1.3V
99 * according to MX53 IC TO2 datasheet.
101 if (is_soc_rev(CHIP_REV_2_0) == 0) {
102 /* Set VCC to 1.3V for TO2 */
103 pmic_reg_read(p, REG_SW_1, &val);
104 val &= ~SWX_OUT_MASK;
106 pmic_reg_write(p, REG_SW_1, val);
108 /* Set VDDA to 1.3V for TO2 */
109 pmic_reg_read(p, REG_SW_2, &val);
110 val &= ~SWX_OUT_MASK;
112 pmic_reg_write(p, REG_SW_2, val);
116 static void setup_iomux_fec(void)
118 static const iomux_v3_cfg_t fec_pads[] = {
119 NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
120 PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
121 NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
122 NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
123 PAD_CTL_HYS | PAD_CTL_PKE),
124 NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
125 PAD_CTL_HYS | PAD_CTL_PKE),
126 NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
127 NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
128 NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
129 NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
130 PAD_CTL_HYS | PAD_CTL_PKE),
131 NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
132 PAD_CTL_HYS | PAD_CTL_PKE),
133 NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
134 PAD_CTL_HYS | PAD_CTL_PKE),
137 imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
140 #ifdef CONFIG_FSL_ESDHC_IMX
141 struct fsl_esdhc_cfg esdhc_cfg[2] = {
142 {MMC_SDHC1_BASE_ADDR},
143 {MMC_SDHC3_BASE_ADDR},
146 int board_mmc_getcd(struct mmc *mmc)
148 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
151 imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA11__GPIO3_11);
152 gpio_direction_input(IMX_GPIO_NR(3, 11));
153 imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA13__GPIO3_13);
154 gpio_direction_input(IMX_GPIO_NR(3, 13));
156 if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
157 ret = !gpio_get_value(IMX_GPIO_NR(3, 13));
159 ret = !gpio_get_value(IMX_GPIO_NR(3, 11));
164 #define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
166 #define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
169 int board_mmc_init(bd_t *bis)
171 static const iomux_v3_cfg_t sd1_pads[] = {
172 NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
173 NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
174 NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
175 NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
176 NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
177 NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
178 MX53_PAD_EIM_DA13__GPIO3_13,
181 static const iomux_v3_cfg_t sd2_pads[] = {
182 NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
184 NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__ESDHC3_CLK, SD_PAD_CTRL),
185 NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__ESDHC3_DAT0, SD_PAD_CTRL),
186 NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__ESDHC3_DAT1, SD_PAD_CTRL),
187 NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__ESDHC3_DAT2, SD_PAD_CTRL),
188 NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__ESDHC3_DAT3, SD_PAD_CTRL),
189 NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__ESDHC3_DAT4, SD_PAD_CTRL),
190 NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__ESDHC3_DAT5, SD_PAD_CTRL),
191 NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__ESDHC3_DAT6, SD_PAD_CTRL),
192 NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__ESDHC3_DAT7, SD_PAD_CTRL),
193 MX53_PAD_EIM_DA11__GPIO3_11,
199 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
200 esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
202 for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
205 imx_iomux_v3_setup_multiple_pads(sd1_pads,
206 ARRAY_SIZE(sd1_pads));
209 imx_iomux_v3_setup_multiple_pads(sd2_pads,
210 ARRAY_SIZE(sd2_pads));
213 printf("Warning: you configured more ESDHC controller"
214 "(%d) as supported by the board(2)\n",
215 CONFIG_SYS_FSL_ESDHC_NUM);
218 ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
227 int board_early_init_f(void)
237 /* address of boot parameters */
238 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
243 #ifdef CONFIG_CMD_BMODE
244 static const struct boot_mode board_boot_modes[] = {
245 /* 4 bit bus width */
246 {"mmc0", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x12)},
247 {"mmc1", MAKE_CFGVAL(0x40, 0x20, 0x08, 0x12)},
252 int board_late_init(void)
257 #ifdef CONFIG_CMD_BMODE
258 add_board_boot_modes(board_boot_modes);
265 puts("Board: MX53EVK\n");