board/freescale/mx53evk/mx53evk.c

   1 /*
   2  * (C) Copyright 2010 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <asm/io.h>
  25 #include <asm/arch/imx-regs.h>
  26 #include <asm/arch/mx5x_pins.h>
  27 #include <asm/arch/sys_proto.h>
  28 #include <asm/arch/crm_regs.h>
  29 #include <asm/arch/iomux.h>
  30 #include <asm/errno.h>
  31 #include <netdev.h>
  32 #include <i2c.h>
  33 #include <mmc.h>
  34 #include <fsl_esdhc.h>
  35 #include <pmic.h>
  36 #include <fsl_pmic.h>
  37 #include <asm/gpio.h>
  38 #include <mc13892.h>
  39
  40 DECLARE_GLOBAL_DATA_PTR;
  41
  42 int dram_init(void)
  43 {
  44         /* dram_init must store complete ramsize in gd->ram_size */
  45         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  46                                 PHYS_SDRAM_1_SIZE);
  47         return 0;
  48 }
  49
  50 static void setup_iomux_uart(void)
  51 {
  52         /* UART1 RXD */
  53         mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_ALT2);
  54         mxc_iomux_set_pad(MX53_PIN_CSI0_D11,
  55                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
  56                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
  57                                 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
  58                                 PAD_CTL_ODE_OPENDRAIN_ENABLE);
  59         mxc_iomux_set_input(MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x1);
  60
  61         /* UART1 TXD */
  62         mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT2);
  63         mxc_iomux_set_pad(MX53_PIN_CSI0_D10,
  64                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
  65                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
  66                                 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
  67                                 PAD_CTL_ODE_OPENDRAIN_ENABLE);
  68 }
  69
  70 static void setup_i2c(unsigned int port_number)
  71 {
  72         switch (port_number) {
  73         case 0:
  74                 /* i2c1 SDA */
  75                 mxc_request_iomux(MX53_PIN_CSI0_D8,
  76                                 IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
  77                 mxc_iomux_set_input(MX53_I2C1_IPP_SDA_IN_SELECT_INPUT,
  78                                 INPUT_CTL_PATH0);
  79                 mxc_iomux_set_pad(MX53_PIN_CSI0_D8,
  80                                 PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
  81                                 PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE |
  82                                 PAD_CTL_ODE_OPENDRAIN_ENABLE);
  83                 /* i2c1 SCL */
  84                 mxc_request_iomux(MX53_PIN_CSI0_D9,
  85                                 IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
  86                 mxc_iomux_set_input(MX53_I2C1_IPP_SCL_IN_SELECT_INPUT,
  87                                 INPUT_CTL_PATH0);
  88                 mxc_iomux_set_pad(MX53_PIN_CSI0_D9,
  89                                 PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
  90                                 PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE |
  91                                 PAD_CTL_ODE_OPENDRAIN_ENABLE);
  92                 break;
  93         case 1:
  94                 /* i2c2 SDA */
  95                 mxc_request_iomux(MX53_PIN_KEY_ROW3,
  96                                 IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION);
  97                 mxc_iomux_set_input(MX53_I2C2_IPP_SDA_IN_SELECT_INPUT,
  98                                 INPUT_CTL_PATH0);
  99                 mxc_iomux_set_pad(MX53_PIN_KEY_ROW3,
 100                                 PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
 101                                 PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE |
 102                                 PAD_CTL_ODE_OPENDRAIN_ENABLE);
 103
 104                 /* i2c2 SCL */
 105                 mxc_request_iomux(MX53_PIN_KEY_COL3,
 106                                 IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION);
 107                 mxc_iomux_set_input(MX53_I2C2_IPP_SCL_IN_SELECT_INPUT,
 108                                 INPUT_CTL_PATH0);
 109                 mxc_iomux_set_pad(MX53_PIN_KEY_COL3,
 110                                 PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
 111                                 PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE |
 112                                 PAD_CTL_ODE_OPENDRAIN_ENABLE);
 113                 break;
 114         default:
 115                 printf("Warning: Wrong I2C port number\n");
 116                 break;
 117         }
 118 }
 119
 120 void power_init(void)
 121 {
 122         unsigned int val;
 123         struct pmic *p;
 124
 125         pmic_init();
 126         p = get_pmic();
 127
 128         /* Set VDDA to 1.25V */
 129         pmic_reg_read(p, REG_SW_2, &val);
 130         val &= ~SWX_OUT_MASK;
 131         val |= SWX_OUT_1_25;
 132         pmic_reg_write(p, REG_SW_2, val);
 133
 134         /*
 135          * Need increase VCC and VDDA to 1.3V
 136          * according to MX53 IC TO2 datasheet.
 137          */
 138         if (is_soc_rev(CHIP_REV_2_0) == 0) {
 139                 /* Set VCC to 1.3V for TO2 */
 140                 pmic_reg_read(p, REG_SW_1, &val);
 141                 val &= ~SWX_OUT_MASK;
 142                 val |= SWX_OUT_1_30;
 143                 pmic_reg_write(p, REG_SW_1, val);
 144
 145                 /* Set VDDA to 1.3V for TO2 */
 146                 pmic_reg_read(p, REG_SW_2, &val);
 147                 val &= ~SWX_OUT_MASK;
 148                 val |= SWX_OUT_1_30;
 149                 pmic_reg_write(p, REG_SW_2, val);
 150         }
 151 }
 152
 153 static void setup_iomux_fec(void)
 154 {
 155         /*FEC_MDIO*/
 156         mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0);
 157         mxc_iomux_set_pad(MX53_PIN_FEC_MDIO,
 158                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 159                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 160                                 PAD_CTL_22K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE);
 161         mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT, 0x1);
 162
 163         /*FEC_MDC*/
 164         mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0);
 165         mxc_iomux_set_pad(MX53_PIN_FEC_MDC, PAD_CTL_DRV_HIGH);
 166
 167         /* FEC RXD1 */
 168         mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0);
 169         mxc_iomux_set_pad(MX53_PIN_FEC_RXD1,
 170                         PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
 171
 172         /* FEC RXD0 */
 173         mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0);
 174         mxc_iomux_set_pad(MX53_PIN_FEC_RXD0,
 175                         PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
 176
 177          /* FEC TXD1 */
 178         mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0);
 179         mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, PAD_CTL_DRV_HIGH);
 180
 181         /* FEC TXD0 */
 182         mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0);
 183         mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, PAD_CTL_DRV_HIGH);
 184
 185         /* FEC TX_EN */
 186         mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0);
 187         mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, PAD_CTL_DRV_HIGH);
 188
 189         /* FEC TX_CLK */
 190         mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0);
 191         mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK,
 192                         PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
 193
 194         /* FEC RX_ER */
 195         mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0);
 196         mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER,
 197                         PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
 198
 199         /* FEC CRS */
 200         mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0);
 201         mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV,
 202                         PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
 203 }
 204
 205 #ifdef CONFIG_FSL_ESDHC
 206 struct fsl_esdhc_cfg esdhc_cfg[2] = {
 207         {MMC_SDHC1_BASE_ADDR, 1},
 208         {MMC_SDHC3_BASE_ADDR, 1},
 209 };
 210
 211 int board_mmc_getcd(struct mmc *mmc)
 212 {
 213         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 214         int ret;
 215
 216         mxc_request_iomux(MX53_PIN_EIM_DA11, IOMUX_CONFIG_ALT1);
 217         gpio_direction_input(75);
 218         mxc_request_iomux(MX53_PIN_EIM_DA13, IOMUX_CONFIG_ALT1);
 219         gpio_direction_input(77);
 220
 221         if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
 222                 ret = !gpio_get_value(77); /* GPIO3_13 */
 223         else
 224                 ret = !gpio_get_value(75); /* GPIO3_11 */
 225
 226         return ret;
 227 }
 228
 229 int board_mmc_init(bd_t *bis)
 230 {
 231         u32 index;
 232         s32 status = 0;
 233
 234         for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
 235                 switch (index) {
 236                 case 0:
 237                         mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
 238                         mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
 239                         mxc_request_iomux(MX53_PIN_SD1_DATA0,
 240                                                 IOMUX_CONFIG_ALT0);
 241                         mxc_request_iomux(MX53_PIN_SD1_DATA1,
 242                                                 IOMUX_CONFIG_ALT0);
 243                         mxc_request_iomux(MX53_PIN_SD1_DATA2,
 244                                                 IOMUX_CONFIG_ALT0);
 245                         mxc_request_iomux(MX53_PIN_SD1_DATA3,
 246                                                 IOMUX_CONFIG_ALT0);
 247                         mxc_request_iomux(MX53_PIN_EIM_DA13,
 248                                                 IOMUX_CONFIG_ALT1);
 249
 250                         mxc_iomux_set_pad(MX53_PIN_SD1_CMD,
 251                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 252                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 253                                 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
 254                         mxc_iomux_set_pad(MX53_PIN_SD1_CLK,
 255                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 256                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
 257                                 PAD_CTL_DRV_HIGH);
 258                         mxc_iomux_set_pad(MX53_PIN_SD1_DATA0,
 259                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 260                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 261                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 262                         mxc_iomux_set_pad(MX53_PIN_SD1_DATA1,
 263                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 264                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 265                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 266                         mxc_iomux_set_pad(MX53_PIN_SD1_DATA2,
 267                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 268                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 269                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 270                         mxc_iomux_set_pad(MX53_PIN_SD1_DATA3,
 271                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 272                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 273                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 274                         break;
 275                 case 1:
 276                         mxc_request_iomux(MX53_PIN_ATA_RESET_B,
 277                                                 IOMUX_CONFIG_ALT2);
 278                         mxc_request_iomux(MX53_PIN_ATA_IORDY,
 279                                                 IOMUX_CONFIG_ALT2);
 280                         mxc_request_iomux(MX53_PIN_ATA_DATA8,
 281                                                 IOMUX_CONFIG_ALT4);
 282                         mxc_request_iomux(MX53_PIN_ATA_DATA9,
 283                                                 IOMUX_CONFIG_ALT4);
 284                         mxc_request_iomux(MX53_PIN_ATA_DATA10,
 285                                                 IOMUX_CONFIG_ALT4);
 286                         mxc_request_iomux(MX53_PIN_ATA_DATA11,
 287                                                 IOMUX_CONFIG_ALT4);
 288                         mxc_request_iomux(MX53_PIN_ATA_DATA0,
 289                                                 IOMUX_CONFIG_ALT4);
 290                         mxc_request_iomux(MX53_PIN_ATA_DATA1,
 291                                                 IOMUX_CONFIG_ALT4);
 292                         mxc_request_iomux(MX53_PIN_ATA_DATA2,
 293                                                 IOMUX_CONFIG_ALT4);
 294                         mxc_request_iomux(MX53_PIN_ATA_DATA3,
 295                                                 IOMUX_CONFIG_ALT4);
 296                         mxc_request_iomux(MX53_PIN_EIM_DA11,
 297                                                 IOMUX_CONFIG_ALT1);
 298
 299                         mxc_iomux_set_pad(MX53_PIN_ATA_RESET_B,
 300                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 301                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 302                                 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
 303                         mxc_iomux_set_pad(MX53_PIN_ATA_IORDY,
 304                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 305                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
 306                                 PAD_CTL_DRV_HIGH);
 307                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA8,
 308                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 309                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 310                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 311                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA9,
 312                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 313                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 314                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 315                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA10,
 316                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 317                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 318                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 319                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA11,
 320                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 321                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 322                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 323                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA0,
 324                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 325                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 326                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 327                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA1,
 328                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 329                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 330                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 331                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA2,
 332                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 333                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 334                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 335                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA3,
 336                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 337                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 338                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 339
 340                         break;
 341                 default:
 342                         printf("Warning: you configured more ESDHC controller"
 343                                 "(%d) as supported by the board(2)\n",
 344                                 CONFIG_SYS_FSL_ESDHC_NUM);
 345                         return status;
 346                 }
 347                 status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
 348         }
 349
 350         return status;
 351 }
 352 #endif
 353
 354 int board_early_init_f(void)
 355 {
 356         setup_iomux_uart();
 357         setup_iomux_fec();
 358
 359         return 0;
 360 }
 361
 362 int board_init(void)
 363 {
 364         /* address of boot parameters */
 365         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 366
 367         return 0;
 368 }
 369
 370 int board_late_init(void)
 371 {
 372         setup_i2c(1);
 373         power_init();
 374
 375         return 0;
 376 }
 377
 378 int checkboard(void)
 379 {
 380         puts("Board: MX53EVK\n");
 381
 382         return 0;
 383 }