2 * (C) Copyright 2009 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/arch/imx-regs.h>
27 #include <asm/arch/mx5x_pins.h>
28 #include <asm/arch/iomux.h>
29 #include <asm/errno.h>
30 #include <asm/arch/sys_proto.h>
31 #include <asm/arch/crm_regs.h>
34 #include <fsl_esdhc.h>
38 #include <usb/ehci-fsl.h>
40 DECLARE_GLOBAL_DATA_PTR;
42 #ifdef CONFIG_FSL_ESDHC
43 struct fsl_esdhc_cfg esdhc_cfg[2] = {
44 {MMC_SDHC1_BASE_ADDR, 1},
45 {MMC_SDHC2_BASE_ADDR, 1},
51 /* dram_init must store complete ramsize in gd->ram_size */
52 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
57 static void setup_iomux_uart(void)
59 unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
60 PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH;
62 mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
63 mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST);
64 mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0);
65 mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST);
66 mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0);
67 mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad);
68 mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0);
69 mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad);
72 static void setup_iomux_fec(void)
75 mxc_request_iomux(MX51_PIN_EIM_EB2 , IOMUX_CONFIG_ALT3);
76 mxc_iomux_set_pad(MX51_PIN_EIM_EB2 , 0x1FD);
79 mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT2);
80 mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, 0x2004);
83 mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT3);
84 mxc_iomux_set_pad(MX51_PIN_EIM_CS3, 0x180);
87 mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT3);
88 mxc_iomux_set_pad(MX51_PIN_EIM_CS2, 0x180);
91 mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT3);
92 mxc_iomux_set_pad(MX51_PIN_EIM_EB3, 0x180);
95 mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT2);
96 mxc_iomux_set_pad(MX51_PIN_NANDF_D9, 0x2180);
99 mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT2);
100 mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, 0x2004);
103 mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT2);
104 mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, 0x2004);
107 mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT2);
108 mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, 0x2004);
111 mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT2);
112 mxc_iomux_set_pad(MX51_PIN_NANDF_D8, 0x2004);
115 mxc_request_iomux(MX51_PIN_NANDF_CS7, IOMUX_CONFIG_ALT1);
116 mxc_iomux_set_pad(MX51_PIN_NANDF_CS7, 0x2004);
119 mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT2);
120 mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, 0x2004);
123 mxc_request_iomux(MX51_PIN_NANDF_RDY_INT, IOMUX_CONFIG_ALT1);
124 mxc_iomux_set_pad(MX51_PIN_NANDF_RDY_INT, 0x2180);
127 mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT1);
128 mxc_iomux_set_pad(MX51_PIN_NANDF_RB2, 0x2180);
131 mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT1);
132 mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, 0x2180);
135 mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT3);
136 mxc_iomux_set_pad(MX51_PIN_EIM_CS5, 0x180);
139 mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT3);
140 mxc_iomux_set_pad(MX51_PIN_EIM_CS4, 0x180);
143 mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT2);
144 mxc_iomux_set_pad(MX51_PIN_NANDF_D11, 0x2180);
147 #ifdef CONFIG_MXC_SPI
148 static void setup_iomux_spi(void)
150 /* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */
151 mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0);
152 mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI, 0x105);
154 /* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */
155 mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0);
156 mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO, 0x105);
158 /* de-select SS1 of instance: ecspi1. */
159 mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT3);
160 mxc_iomux_set_pad(MX51_PIN_CSPI1_SS1, 0x85);
162 /* 000: Select mux mode: ALT0 mux port: SS0 ecspi1 */
163 mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT0);
164 mxc_iomux_set_pad(MX51_PIN_CSPI1_SS0, 0x185);
166 /* 000: Select mux mode: ALT0 mux port: RDY of instance: ecspi1. */
167 mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT0);
168 mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY, 0x180);
170 /* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */
171 mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0);
172 mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK, 0x105);
176 #ifdef CONFIG_USB_EHCI_MX5
177 #define MX51EVK_USBH1_HUB_RST IOMUX_TO_GPIO(MX51_PIN_GPIO1_7) /* GPIO1_7 */
178 #define MX51EVK_USBH1_STP IOMUX_TO_GPIO(MX51_PIN_USBH1_STP) /* GPIO1_27 */
179 #define MX51EVK_USB_CLK_EN_B IOMUX_TO_GPIO(MX51_PIN_EIM_D18) /* GPIO2_1 */
180 #define MX51EVK_USB_PHY_RESET IOMUX_TO_GPIO(MX51_PIN_EIM_D21) /* GPIO2_5 */
182 #define USBH1_PAD (PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | \
183 PAD_CTL_100K_PU | PAD_CTL_PUE_PULL | \
184 PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE)
185 #define GPIO_PAD (PAD_CTL_DRV_HIGH | PAD_CTL_PKE_ENABLE | \
187 #define NO_PAD (1 << 16)
189 static void setup_usb_h1(void)
191 setup_iomux_usb_h1();
193 /* GPIO_1_7 for USBH1 hub reset */
194 mxc_request_iomux(MX51_PIN_GPIO1_7, IOMUX_CONFIG_ALT0);
195 mxc_iomux_set_pad(MX51_PIN_GPIO1_7, NO_PAD);
198 mxc_request_iomux(MX51_PIN_EIM_D17, IOMUX_CONFIG_ALT1);
199 mxc_iomux_set_pad(MX51_PIN_EIM_D17, GPIO_PAD);
201 /* GPIO_2_5 for USB PHY reset */
202 mxc_request_iomux(MX51_PIN_EIM_D21, IOMUX_CONFIG_ALT1);
203 mxc_iomux_set_pad(MX51_PIN_EIM_D21, GPIO_PAD);
206 int board_ehci_hcd_init(int port)
208 /* Set USBH1_STP to GPIO and toggle it */
209 mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_GPIO);
210 mxc_iomux_set_pad(MX51_PIN_USBH1_STP, USBH1_PAD);
212 gpio_direction_output(MX51EVK_USBH1_STP, 0);
213 gpio_direction_output(MX51EVK_USB_PHY_RESET, 0);
215 gpio_set_value(MX51EVK_USBH1_STP, 1);
217 /* Set back USBH1_STP to be function */
218 mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_ALT0);
219 mxc_iomux_set_pad(MX51_PIN_USBH1_STP, USBH1_PAD);
221 /* De-assert USB PHY RESETB */
222 gpio_set_value(MX51EVK_USB_PHY_RESET, 1);
224 /* Drive USB_CLK_EN_B line low */
225 gpio_direction_output(MX51EVK_USB_CLK_EN_B, 0);
228 gpio_direction_output(MX51EVK_USBH1_HUB_RST, 0);
230 gpio_set_value(MX51EVK_USBH1_HUB_RST, 1);
235 static void power_init(void)
238 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
244 /* Write needed to Power Gate 2 register */
245 pmic_reg_read(p, REG_POWER_MISC, &val);
247 pmic_reg_write(p, REG_POWER_MISC, val);
249 /* Externally powered */
250 pmic_reg_read(p, REG_CHARGE, &val);
251 val |= ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | CHGAUTOB;
252 pmic_reg_write(p, REG_CHARGE, val);
254 /* power up the system first */
255 pmic_reg_write(p, REG_POWER_MISC, PWUP);
257 /* Set core voltage to 1.1V */
258 pmic_reg_read(p, REG_SW_0, &val);
259 val = (val & ~SWx_VOLT_MASK) | SWx_1_100V;
260 pmic_reg_write(p, REG_SW_0, val);
262 /* Setup VCC (SW2) to 1.25 */
263 pmic_reg_read(p, REG_SW_1, &val);
264 val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
265 pmic_reg_write(p, REG_SW_1, val);
267 /* Setup 1V2_DIG1 (SW3) to 1.25 */
268 pmic_reg_read(p, REG_SW_2, &val);
269 val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
270 pmic_reg_write(p, REG_SW_2, val);
273 /* Raise the core frequency to 800MHz */
274 writel(0x0, &mxc_ccm->cacrr);
276 /* Set switchers in Auto in NORMAL mode & STANDBY mode */
277 /* Setup the switcher mode for SW1 & SW2*/
278 pmic_reg_read(p, REG_SW_4, &val);
279 val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
280 (SWMODE_MASK << SWMODE2_SHIFT)));
281 val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
282 (SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
283 pmic_reg_write(p, REG_SW_4, val);
285 /* Setup the switcher mode for SW3 & SW4 */
286 pmic_reg_read(p, REG_SW_5, &val);
287 val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) |
288 (SWMODE_MASK << SWMODE4_SHIFT)));
289 val |= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) |
290 (SWMODE_AUTO_AUTO << SWMODE4_SHIFT);
291 pmic_reg_write(p, REG_SW_5, val);
293 /* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.6V */
294 pmic_reg_read(p, REG_SETTING_0, &val);
295 val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK);
296 val |= VDIG_1_65 | VGEN3_1_8 | VCAM_2_6;
297 pmic_reg_write(p, REG_SETTING_0, val);
299 /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
300 pmic_reg_read(p, REG_SETTING_1, &val);
301 val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
302 val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775;
303 pmic_reg_write(p, REG_SETTING_1, val);
305 /* Configure VGEN3 and VCAM regulators to use external PNP */
306 val = VGEN3CONFIG | VCAMCONFIG;
307 pmic_reg_write(p, REG_MODE_1, val);
310 /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
311 val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
312 VVIDEOEN | VAUDIOEN | VSDEN;
313 pmic_reg_write(p, REG_MODE_1, val);
315 mxc_request_iomux(MX51_PIN_EIM_A20, IOMUX_CONFIG_ALT1);
316 gpio_direction_output(46, 0);
320 gpio_set_value(46, 1);
323 #ifdef CONFIG_FSL_ESDHC
324 int board_mmc_getcd(u8 *cd, struct mmc *mmc)
326 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
328 mxc_request_iomux(MX51_PIN_GPIO1_0, IOMUX_CONFIG_ALT1);
329 mxc_request_iomux(MX51_PIN_GPIO1_6, IOMUX_CONFIG_ALT0);
331 if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
332 *cd = gpio_get_value(0);
334 *cd = gpio_get_value(6);
339 int board_mmc_init(bd_t *bis)
344 for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM;
348 mxc_request_iomux(MX51_PIN_SD1_CMD,
349 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
350 mxc_request_iomux(MX51_PIN_SD1_CLK,
351 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
352 mxc_request_iomux(MX51_PIN_SD1_DATA0,
353 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
354 mxc_request_iomux(MX51_PIN_SD1_DATA1,
355 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
356 mxc_request_iomux(MX51_PIN_SD1_DATA2,
357 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
358 mxc_request_iomux(MX51_PIN_SD1_DATA3,
359 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
360 mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
361 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
362 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
364 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
365 mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
366 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
367 PAD_CTL_HYS_NONE | PAD_CTL_47K_PU |
369 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
370 mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
371 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
372 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
374 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
375 mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
376 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
377 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
379 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
380 mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
381 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
382 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
384 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
385 mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
386 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
387 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PD |
389 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
390 mxc_request_iomux(MX51_PIN_GPIO1_0,
391 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
392 mxc_iomux_set_pad(MX51_PIN_GPIO1_0,
394 mxc_request_iomux(MX51_PIN_GPIO1_1,
395 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
396 mxc_iomux_set_pad(MX51_PIN_GPIO1_1,
400 mxc_request_iomux(MX51_PIN_SD2_CMD,
401 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
402 mxc_request_iomux(MX51_PIN_SD2_CLK,
403 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
404 mxc_request_iomux(MX51_PIN_SD2_DATA0,
406 mxc_request_iomux(MX51_PIN_SD2_DATA1,
408 mxc_request_iomux(MX51_PIN_SD2_DATA2,
410 mxc_request_iomux(MX51_PIN_SD2_DATA3,
412 mxc_iomux_set_pad(MX51_PIN_SD2_CMD,
413 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
415 mxc_iomux_set_pad(MX51_PIN_SD2_CLK,
416 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
418 mxc_iomux_set_pad(MX51_PIN_SD2_DATA0,
419 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
421 mxc_iomux_set_pad(MX51_PIN_SD2_DATA1,
422 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
424 mxc_iomux_set_pad(MX51_PIN_SD2_DATA2,
425 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
427 mxc_iomux_set_pad(MX51_PIN_SD2_DATA3,
428 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
430 mxc_request_iomux(MX51_PIN_SD2_CMD,
431 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
432 mxc_request_iomux(MX51_PIN_GPIO1_6,
433 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
434 mxc_iomux_set_pad(MX51_PIN_GPIO1_6,
436 mxc_request_iomux(MX51_PIN_GPIO1_5,
437 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
438 mxc_iomux_set_pad(MX51_PIN_GPIO1_5,
442 printf("Warning: you configured more ESDHC controller"
443 "(%d) as supported by the board(2)\n",
444 CONFIG_SYS_FSL_ESDHC_NUM);
447 status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
453 int board_early_init_f(void)
457 #ifdef CONFIG_USB_EHCI_MX5
466 /* address of boot parameters */
467 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
472 #ifdef CONFIG_BOARD_LATE_INIT
473 int board_late_init(void)
475 #ifdef CONFIG_MXC_SPI
485 puts("Board: MX51EVK\n");