2 * (C) Copyright 2009 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/arch/imx-regs.h>
26 #include <asm/arch/mx51_pins.h>
27 #include <asm/arch/iomux.h>
28 #include <asm/errno.h>
29 #include <asm/arch/sys_proto.h>
30 #include <asm/arch/crm_regs.h>
33 #include <fsl_esdhc.h>
38 DECLARE_GLOBAL_DATA_PTR;
40 static u32 system_rev;
41 struct io_board_ctrl *mx51_io_board;
43 #ifdef CONFIG_FSL_ESDHC
44 struct fsl_esdhc_cfg esdhc_cfg[2] = {
45 {MMC_SDHC1_BASE_ADDR, 1},
46 {MMC_SDHC2_BASE_ADDR, 1},
50 u32 get_board_rev(void)
57 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
58 gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1,
63 static void setup_iomux_uart(void)
65 unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
66 PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH;
68 mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
69 mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST);
70 mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0);
71 mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST);
72 mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0);
73 mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad);
74 mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0);
75 mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad);
78 static void setup_iomux_fec(void)
81 mxc_request_iomux(MX51_PIN_EIM_EB2 , IOMUX_CONFIG_ALT3);
82 mxc_iomux_set_pad(MX51_PIN_EIM_EB2 , 0x1FD);
85 mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT2);
86 mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, 0x2004);
89 mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT3);
90 mxc_iomux_set_pad(MX51_PIN_EIM_CS3, 0x180);
93 mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT3);
94 mxc_iomux_set_pad(MX51_PIN_EIM_CS2, 0x180);
97 mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT3);
98 mxc_iomux_set_pad(MX51_PIN_EIM_EB3, 0x180);
101 mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT2);
102 mxc_iomux_set_pad(MX51_PIN_NANDF_D9, 0x2180);
105 mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT2);
106 mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, 0x2004);
109 mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT2);
110 mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, 0x2004);
113 mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT2);
114 mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, 0x2004);
117 mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT2);
118 mxc_iomux_set_pad(MX51_PIN_NANDF_D8, 0x2004);
121 mxc_request_iomux(MX51_PIN_NANDF_CS7, IOMUX_CONFIG_ALT1);
122 mxc_iomux_set_pad(MX51_PIN_NANDF_CS7, 0x2004);
125 mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT2);
126 mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, 0x2004);
129 mxc_request_iomux(MX51_PIN_NANDF_RDY_INT, IOMUX_CONFIG_ALT1);
130 mxc_iomux_set_pad(MX51_PIN_NANDF_RDY_INT, 0x2180);
133 mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT1);
134 mxc_iomux_set_pad(MX51_PIN_NANDF_RB2, 0x2180);
137 mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT1);
138 mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, 0x2180);
141 mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT3);
142 mxc_iomux_set_pad(MX51_PIN_EIM_CS5, 0x180);
145 mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT3);
146 mxc_iomux_set_pad(MX51_PIN_EIM_CS4, 0x180);
149 mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT2);
150 mxc_iomux_set_pad(MX51_PIN_NANDF_D11, 0x2180);
153 #ifdef CONFIG_MXC_SPI
154 static void setup_iomux_spi(void)
156 /* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */
157 mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0);
158 mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI, 0x105);
160 /* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */
161 mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0);
162 mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO, 0x105);
164 /* de-select SS1 of instance: ecspi1. */
165 mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT3);
166 mxc_iomux_set_pad(MX51_PIN_CSPI1_SS1, 0x85);
168 /* 000: Select mux mode: ALT0 mux port: SS0 ecspi1 */
169 mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT0);
170 mxc_iomux_set_pad(MX51_PIN_CSPI1_SS0, 0x185);
172 /* 000: Select mux mode: ALT0 mux port: RDY of instance: ecspi1. */
173 mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT0);
174 mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY, 0x180);
176 /* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */
177 mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0);
178 mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK, 0x105);
182 static void power_init(void)
186 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
188 /* Write needed to Power Gate 2 register */
189 val = pmic_reg_read(REG_POWER_MISC);
191 pmic_reg_write(REG_POWER_MISC, val);
193 /* Write needed to update Charger 0 */
194 pmic_reg_write(REG_CHARGE, VCHRG0 | VCHRG1 | VCHRG2 |
195 ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | ICHRGTR0 |
196 OVCTRL1 | UCHEN | CHRGLEDEN | CYCLB);
198 /* power up the system first */
199 pmic_reg_write(REG_POWER_MISC, PWUP);
201 /* Set core voltage to 1.1V */
202 val = pmic_reg_read(REG_SW_0);
203 val = (val & (~0x1F)) | 0x14;
204 pmic_reg_write(REG_SW_0, val);
206 /* Setup VCC (SW2) to 1.25 */
207 val = pmic_reg_read(REG_SW_1);
208 val = (val & (~0x1F)) | 0x1A;
209 pmic_reg_write(REG_SW_1, val);
211 /* Setup 1V2_DIG1 (SW3) to 1.25 */
212 val = pmic_reg_read(REG_SW_2);
213 val = (val & (~0x1F)) | 0x1A;
214 pmic_reg_write(REG_SW_2, val);
217 /* Raise the core frequency to 800MHz */
218 writel(0x0, &mxc_ccm->cacrr);
220 /* Set switchers in Auto in NORMAL mode & STANDBY mode */
221 /* Setup the switcher mode for SW1 & SW2*/
222 val = pmic_reg_read(REG_SW_4);
223 val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
224 (SWMODE_MASK << SWMODE2_SHIFT)));
225 val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
226 (SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
227 pmic_reg_write(REG_SW_4, val);
229 /* Setup the switcher mode for SW3 & SW4 */
230 val = pmic_reg_read(REG_SW_5);
231 val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) |
232 (SWMODE_MASK << SWMODE4_SHIFT)));
233 val |= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) |
234 (SWMODE_AUTO_AUTO << SWMODE4_SHIFT);
235 pmic_reg_write(REG_SW_5, val);
237 /* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.6V */
238 val = pmic_reg_read(REG_SETTING_0);
239 val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK);
240 val |= VDIG_1_65 | VGEN3_1_8 | VCAM_2_6;
241 pmic_reg_write(REG_SETTING_0, val);
243 /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
244 val = pmic_reg_read(REG_SETTING_1);
245 val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
246 val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775;
247 pmic_reg_write(REG_SETTING_1, val);
249 /* Configure VGEN3 and VCAM regulators to use external PNP */
250 val = VGEN3CONFIG | VCAMCONFIG;
251 pmic_reg_write(REG_MODE_1, val);
254 reg = readl(GPIO2_BASE_ADDR + 0x0);
255 reg &= ~0x4000; /* Lower reset line */
256 writel(reg, GPIO2_BASE_ADDR + 0x0);
258 reg = readl(GPIO2_BASE_ADDR + 0x4);
259 reg |= 0x4000; /* configure GPIO lines as output */
260 writel(reg, GPIO2_BASE_ADDR + 0x4);
262 /* Reset the ethernet controller over GPIO */
263 writel(0x1, IOMUXC_BASE_ADDR + 0x0AC);
265 /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
266 val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
267 VVIDEOEN | VAUDIOEN | VSDEN;
268 pmic_reg_write(REG_MODE_1, val);
272 reg = readl(GPIO2_BASE_ADDR + 0x0);
274 writel(reg, GPIO2_BASE_ADDR + 0x0);
277 #ifdef CONFIG_FSL_ESDHC
278 int board_mmc_getcd(u8 *cd, struct mmc *mmc)
280 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
282 if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
283 *cd = readl(GPIO1_BASE_ADDR) & 0x01;
285 *cd = readl(GPIO1_BASE_ADDR) & 0x40;
290 int board_mmc_init(bd_t *bis)
295 for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM;
299 mxc_request_iomux(MX51_PIN_SD1_CMD,
300 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
301 mxc_request_iomux(MX51_PIN_SD1_CLK,
302 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
303 mxc_request_iomux(MX51_PIN_SD1_DATA0,
304 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
305 mxc_request_iomux(MX51_PIN_SD1_DATA1,
306 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
307 mxc_request_iomux(MX51_PIN_SD1_DATA2,
308 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
309 mxc_request_iomux(MX51_PIN_SD1_DATA3,
310 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
311 mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
312 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
313 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
315 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
316 mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
317 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
318 PAD_CTL_HYS_NONE | PAD_CTL_47K_PU |
320 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
321 mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
322 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
323 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
325 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
326 mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
327 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
328 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
330 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
331 mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
332 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
333 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
335 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
336 mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
337 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
338 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PD |
340 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
341 mxc_request_iomux(MX51_PIN_GPIO1_0,
342 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
343 mxc_iomux_set_pad(MX51_PIN_GPIO1_0,
345 mxc_request_iomux(MX51_PIN_GPIO1_1,
346 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
347 mxc_iomux_set_pad(MX51_PIN_GPIO1_1,
351 mxc_request_iomux(MX51_PIN_SD2_CMD,
352 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
353 mxc_request_iomux(MX51_PIN_SD2_CLK,
354 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
355 mxc_request_iomux(MX51_PIN_SD2_DATA0,
357 mxc_request_iomux(MX51_PIN_SD2_DATA1,
359 mxc_request_iomux(MX51_PIN_SD2_DATA2,
361 mxc_request_iomux(MX51_PIN_SD2_DATA3,
363 mxc_iomux_set_pad(MX51_PIN_SD2_CMD,
364 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
366 mxc_iomux_set_pad(MX51_PIN_SD2_CLK,
367 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
369 mxc_iomux_set_pad(MX51_PIN_SD2_DATA0,
370 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
372 mxc_iomux_set_pad(MX51_PIN_SD2_DATA1,
373 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
375 mxc_iomux_set_pad(MX51_PIN_SD2_DATA2,
376 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
378 mxc_iomux_set_pad(MX51_PIN_SD2_DATA3,
379 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
381 mxc_request_iomux(MX51_PIN_SD2_CMD,
382 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
383 mxc_request_iomux(MX51_PIN_GPIO1_6,
384 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
385 mxc_iomux_set_pad(MX51_PIN_GPIO1_6,
387 mxc_request_iomux(MX51_PIN_GPIO1_5,
388 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
389 mxc_iomux_set_pad(MX51_PIN_GPIO1_5,
393 printf("Warning: you configured more ESDHC controller"
394 "(%d) as supported by the board(2)\n",
395 CONFIG_SYS_FSL_ESDHC_NUM);
398 status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
406 system_rev = get_cpu_rev();
408 gd->bd->bi_arch_number = MACH_TYPE_MX51_BABBAGE;
409 /* address of boot parameters */
410 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
418 #ifdef BOARD_LATE_INIT
419 int board_late_init(void)
421 #ifdef CONFIG_MXC_SPI
431 puts("Board: MX51EVK ");
433 switch (system_rev & 0xff) {
452 switch (__raw_readl(SRC_BASE_ADDR + 0x8)) {