1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
5 * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
9 #include <asm/arch/imx-regs.h>
10 #include <generated/asm-offsets.h>
12 #include <asm/arch/lowlevel_macro.S>
20 .macro check_soc_version ret, tmp
21 ldr \tmp, =IIM_BASE_ADDR
22 ldr \ret, [\tmp, #IIM_SREV]
24 moveq \tmp, #ROMPATCH_REV
26 moveq \ret, \ret, lsl #4
27 addne \ret, \ret, #0x10
30 /* CPLD on CS5 setup */
31 .macro init_debug_board
32 ldr r0, =DBG_BASE_ADDR
33 ldr r1, =DBG_CSCR_U_CONFIG
35 ldr r1, =DBG_CSCR_L_CONFIG
37 ldr r1, =DBG_CSCR_A_CONFIG
43 ldr r0, =CCM_BASE_ADDR
45 /* default CLKO to 1/32 of the ARM core*/
46 ldr r1, [r0, #CLKCTL_COSR]
47 bic r1, r1, #0x00000FF00
48 bic r1, r1, #0x0000000FF
52 str r1, [r0, #CLKCTL_COSR]
54 ldr r2, =CCM_CCMR_CONFIG
55 str r2, [r0, #CLKCTL_CCMR]
57 check_soc_version r1, r2
59 ldrhs r3, =CCM_MPLL_532_HZ
61 ldr r2, [r0, #CLKCTL_PDR0]
62 tst r2, #CLKMODE_CONSUMER
63 ldrne r3, =CCM_MPLL_532_HZ /* consumer path*/
64 ldreq r3, =CCM_MPLL_399_HZ /* auto path*/
66 str r3, [r0, #CLKCTL_MPCTL]
68 ldr r1, =CCM_PPLL_300_HZ
69 str r1, [r0, #CLKCTL_PPCTL]
71 ldr r1, =CCM_PDR0_CONFIG
73 str r1, [r0, #CLKCTL_PDR0]
75 ldr r1, [r0, #CLKCTL_CGR0]
76 orr r1, r1, #0x0C300000
77 str r1, [r0, #CLKCTL_CGR0]
79 ldr r1, [r0, #CLKCTL_CGR1]
80 orr r1, r1, #0x00000C00
81 orr r1, r1, #0x00000003
82 str r1, [r0, #CLKCTL_CGR1]
84 ldr r1, [r0, #CLKCTL_CGR2]
85 orr r1, r1, #0x00C00000
86 str r1, [r0, #CLKCTL_CGR2]
90 ldr r0, =ESDCTL_BASE_ADDR
95 /*ip(r12) has used to save lr register in upper calling*/
100 mov r1, #CSD0_BASE_ADDR
105 mov r1, #CSD1_BASE_ADDR
111 ldr r3, =ESDCTL_DELAY_LINE5
130 cmp pc, #PHYS_SDRAM_1
132 cmp pc, #(PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)
145 * r0: ESDCTL control base, r1: sdram slot base
146 * r2: DDR type(0:DDR2, 1:MDDR) r3, r4:working base
151 orreq r3, r3, #0x300 /*DDR2*/
162 ldreq r3, =ESDCTL_DDR2_CONFIG
163 ldrne r3, =ESDCTL_MDDR_CONFIG
164 cmp r1, #CSD1_BASE_ADDR
168 ldr r3, =ESDCTL_0x92220000
172 ldr r4, =ESDCTL_PRECHARGE
178 cmp r1, #CSD1_BASE_ADDR
179 ldr r3, =ESDCTL_0xB2220000
183 ldr r4, =ESDCTL_DDR2_EMR2
185 ldr r4, =ESDCTL_DDR2_EMR3
187 ldr r4, =ESDCTL_DDR2_EN_DLL
189 ldr r4, =ESDCTL_DDR2_RESET_DLL
192 ldr r3, =ESDCTL_0x92220000
196 ldr r4, =ESDCTL_PRECHARGE
200 cmp r1, #CSD1_BASE_ADDR
201 ldr r3, =ESDCTL_0xA2220000
208 ldr r3, =ESDCTL_0xB2220000
212 ldreq r4, =ESDCTL_DDR2_MR
213 ldrne r4, =ESDCTL_MDDR_MR
216 ldreq r4, =ESDCTL_DDR2_OCD_DEFAULT
218 ldreq r4, =ESDCTL_DDR2_EN_DLL
219 ldrne r4, =ESDCTL_MDDR_EMR
222 cmp r1, #CSD1_BASE_ADDR
223 ldr r3, =ESDCTL_0x82228080