2 * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/arch/clock.h>
27 #include <asm/arch/imx-regs.h>
28 #include <asm/arch/sys_proto.h>
30 DECLARE_GLOBAL_DATA_PTR;
34 /* dram_init must store complete ramsize in gd->ram_size */
35 gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1,
40 int board_early_init_f(void)
46 * CS0L and CS0A values are from the RedBoot sources by Freescale
47 * and are also equal to those used by Sascha Hauer for the Phytec
48 * i.MX31 board. CS0U is just a slightly optimized hardware default:
49 * the only non-zero field "Wait State Control" is set to half the
52 static const struct mxc_weimcs cs0 = {
53 /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
54 CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 0, 15, 0, 0, 0),
55 /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
56 CSCR_L(1, 0, 0, 0, 0, 1, 5, 0, 0, 0, 1, 1),
57 /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
58 CSCR_A(0, 0, 7, 2, 0, 0, 2, 1, 0, 0, 0, 0, 0, 0)
61 mxc_setup_weimcs(0, &cs0);
63 /* setup pins for UART1 */
64 mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
65 mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
66 mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
67 mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
70 mx31_gpio_mux(MUX_CSPI2_SS2__CSPI2_SS2_B);
71 mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK);
72 mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B);
73 mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI);
74 mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO);
75 mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B);
76 mx31_gpio_mux(MUX_CSPI2_SS1__CSPI2_SS1_B);
78 /* start SPI2 clock */
79 __REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 4);
82 /* Enable UART transceivers also reset the Ethernet/external UART */
85 writew(0x8023, CS4_BASE + 4);
87 /* RedBoot also has an empty loop with 100000 iterations here -
88 * clock doesn't run yet */
89 for (i = 0; i < 100000; i++)
92 /* Clear the reset, toggle the LEDs */
93 writew(0xDF, CS4_BASE + 6);
95 /* clock still doesn't run */
96 for (i = 0; i < 100000; i++)
99 /* See 1.5.4 in IMX31ADSE_PERI_BUS_CNTRL_CPLD_RM.pdf */
110 gd->bd->bi_boot_params = 0x80000100; /* adress of boot parameters */
117 printf("Board: MX31ADS\n");
121 #ifdef CONFIG_CMD_NET
122 int board_eth_init(bd_t *bis)
126 rc = cs8900_initialize(0, CONFIG_CS8900_BASE);