2 * Copyright 2006, 2007 Freescale Semiconductor.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/processor.h>
26 #include <asm/immap_86xx.h>
27 #include <asm/immap_fsl_pci.h>
28 #include <asm/fsl_ddr_sdram.h>
31 #include <fdt_support.h>
34 #include "../common/pixis.h"
36 long int fixed_sdram(void);
38 int board_early_init_f(void)
45 printf ("Board: MPC8641HPCN, System ID: 0x%02x, "
46 "System Version: 0x%02x, FPGA Version: 0x%02x\n",
47 in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
48 in8(PIXIS_BASE + PIXIS_PVER));
54 initdram(int board_type)
58 #if defined(CONFIG_SPD_EEPROM)
59 dram_size = fsl_ddr_sdram();
61 dram_size = fixed_sdram();
64 #if defined(CONFIG_SYS_RAMBOOT)
74 #if !defined(CONFIG_SPD_EEPROM)
76 * Fixed sdram init -- doesn't use serial presence detect.
81 #if !defined(CONFIG_SYS_RAMBOOT)
82 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
83 volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
85 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
86 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
87 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
88 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
89 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
90 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
91 ddr->sdram_mode_1 = CONFIG_SYS_DDR_MODE_1;
92 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
93 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
94 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
95 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
96 ddr->sdram_ocd_cntl = CONFIG_SYS_DDR_OCD_CTRL;
97 ddr->sdram_ocd_status = CONFIG_SYS_DDR_OCD_STATUS;
99 #if defined (CONFIG_DDR_ECC)
100 ddr->err_disable = 0x0000008D;
101 ddr->err_sbe = 0x00ff0000;
107 #if defined (CONFIG_DDR_ECC)
108 /* Enable ECC checking */
109 ddr->sdram_cfg_1 = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
111 ddr->sdram_cfg_1 = CONFIG_SYS_DDR_CONTROL;
112 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
118 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
120 #endif /* !defined(CONFIG_SPD_EEPROM) */
123 #if defined(CONFIG_PCI)
125 * Initialize PCI Devices, report devices found.
128 #ifndef CONFIG_PCI_PNP
129 static struct pci_config_table pci_fsl86xxads_config_table[] = {
130 {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
131 PCI_IDSEL_NUMBER, PCI_ANY_ID,
132 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
134 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}},
140 static struct pci_controller pci1_hose = {
141 #ifndef CONFIG_PCI_PNP
142 config_table:pci_mpc86xxcts_config_table
145 #endif /* CONFIG_PCI */
148 static struct pci_controller pci2_hose;
149 #endif /* CONFIG_PCI2 */
151 int first_free_busno = 0;
153 extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
154 extern void fsl_pci_init(struct pci_controller *hose);
156 void pci_init_board(void)
158 volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
159 volatile ccsr_gur_t *gur = &immap->im_gur;
160 uint devdisr = gur->devdisr;
161 uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL)
162 >> MPC8641_PORDEVSR_IO_SEL_SHIFT;
166 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
167 struct pci_controller *hose = &pci1_hose;
168 struct pci_region *r = hose->regions;
171 uint host1_agent = (gur->porbmsr & MPC8641_PORBMSR_HA)
172 >> MPC8641_PORBMSR_HA_SHIFT;
173 uint pex1_agent = (host1_agent == 0) || (host1_agent == 1);
175 if ((io_sel == 2 || io_sel == 3 || io_sel == 5
176 || io_sel == 6 || io_sel == 7 || io_sel == 0xF)
177 && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
178 debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host");
179 debug("0x%08x=0x%08x ", &pci->pme_msg_det, pci->pme_msg_det);
180 if (pci->pme_msg_det) {
181 pci->pme_msg_det = 0xffffffff;
182 debug(" with errors. Clearing. Now 0x%08x",
188 r += fsl_pci_setup_inbound_windows(r);
190 /* outbound memory */
192 CONFIG_SYS_PCI1_MEM_BASE,
193 CONFIG_SYS_PCI1_MEM_PHYS,
194 CONFIG_SYS_PCI1_MEM_SIZE,
199 CONFIG_SYS_PCI1_IO_BASE,
200 CONFIG_SYS_PCI1_IO_PHYS,
201 CONFIG_SYS_PCI1_IO_SIZE,
204 hose->region_count = r - hose->regions;
206 hose->first_busno=first_free_busno;
207 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
211 first_free_busno=hose->last_busno+1;
212 printf (" PCI-EXPRESS 1 on bus %02x - %02x\n",
213 hose->first_busno,hose->last_busno);
216 * Activate ULI1575 legacy chip by performing a fake
217 * memory access. Needed to make ULI RTC work.
219 in_be32((unsigned *) ((char *)(CONFIG_SYS_PCI1_MEM_BASE
220 + CONFIG_SYS_PCI1_MEM_SIZE - 0x1000000)));
223 puts("PCI-EXPRESS 1: Disabled\n");
227 puts("PCI-EXPRESS1: Disabled\n");
228 #endif /* CONFIG_PCI1 */
232 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI2_ADDR;
233 struct pci_controller *hose = &pci2_hose;
234 struct pci_region *r = hose->regions;
237 r += fsl_pci_setup_inbound_windows(r);
239 /* outbound memory */
241 CONFIG_SYS_PCI2_MEM_BASE,
242 CONFIG_SYS_PCI2_MEM_PHYS,
243 CONFIG_SYS_PCI2_MEM_SIZE,
248 CONFIG_SYS_PCI2_IO_BASE,
249 CONFIG_SYS_PCI2_IO_PHYS,
250 CONFIG_SYS_PCI2_IO_SIZE,
253 hose->region_count = r - hose->regions;
255 hose->first_busno=first_free_busno;
256 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
260 first_free_busno=hose->last_busno+1;
261 printf (" PCI-EXPRESS 2 on bus %02x - %02x\n",
262 hose->first_busno,hose->last_busno);
265 puts("PCI-EXPRESS 2: Disabled\n");
266 #endif /* CONFIG_PCI2 */
271 #if defined(CONFIG_OF_BOARD_SETUP)
272 extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
273 struct pci_controller *hose);
276 ft_board_setup(void *blob, bd_t *bd)
278 ft_cpu_setup(blob, bd);
281 ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
284 ft_fsl_pci_setup(blob, "pci1", &pci2_hose);
292 * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
296 get_board_sys_clk(ulong dummy)
298 u8 i, go_bit, rd_clks;
301 go_bit = in8(PIXIS_BASE + PIXIS_VCTL);
304 rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0);
308 * Only if both go bit and the SCLK bit in VCFGEN0 are set
309 * should we be using the AUX register. Remember, we also set the
310 * GO bit to boot from the alternate bank on the on-board flash
315 i = in8(PIXIS_BASE + PIXIS_AUX);
317 i = in8(PIXIS_BASE + PIXIS_SPD);
319 i = in8(PIXIS_BASE + PIXIS_SPD);
354 int board_eth_init(bd_t *bis)
356 /* Initialize TSECs */
358 return pci_eth_init(bis);